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* Close GitHub PRs and issues automaticallyFelix Singer2022-04-281-0/+36
| | | | | | | | | | | | | The flashrom project does not use GitHub for pull requests or issues. Thus, close issues and pull requests automatically using a GitHub Actions hook. Also, add a comment pointing to our guidelines. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I8076f0fb964970ffd05f355b9d1e33a65aa7a3c8 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Unify timeouts across all SPI operations to 30sSubrata Banik2022-04-271-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument in favor of a fixed timeout of `30 seconds` for any given SPI operation as recommended by the SPI programming guide. Document: Alder Lake-P Client Platform SPI Programming Guide Rev 1.30 (supporting document for multi-master accessing the SPI Flash device.) Refer to below section to understand the problem in more detail and SPI operation timeout recommendation from Intel in multi-master scenarios. On Intel Chipsets that support multi-mastering access of the SPI flash may run into a timeout failure when the operation initiated from a single master just follows the SPI operational timeout recommendation as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR specification, table 9.7). In the multi-master SPI accessing scenario using hardware sequencing operation, it's impossible to know the actual status of the SPI bus prior to individual master starting the operation (SPI Cycle In Progress a.k.a SCIP bit represents the status of SPI operation on individual master). Thus, any SPI operation triggered in multi-master environment might need to account a worst case scenario where the most time consuming operation might have occupied the SPI bus from a master and an operation initiated by another master just timed out. Here is the timeout calculation for any hardware sequencing operation: Worst Case Operational Delay = (Maximum Time consumed by a SPI operation + Any marginal adjustment) Timeout Recommendation for Hardware Sequencing Operation = ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) + Current Operational latency) Assume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC, GbE and other reserved etc, hence, the Timeout Calculation for SPI erase Operation would look like as below: Maximum Time consumed by a SPI Operation = 5 seconds Worst Case Operational Delay = 5 seconds Timeout Recommendation for Hardware Seq Operation = 5 seconds * (6 - 1) + 5 seconds = 30 seconds BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: mark IS25LP064 as TEST_OK_PREWSimon Buhrow2022-04-241-1/+1
| | | | | | | | | | | | Tested '-w', '-E' and '-r' successfully with my FT2232H programmer. Change-Id: I2197ce0be9db7c3d74b24c7445dc06238584ffea Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58472 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Mark GD25Q40(B) as testedSimon Buhrow2022-04-241-1/+1
| | | | | | | | | | | | As mentioned by Wolf Dieter Brandt in his mail from 07.Feb.22. Change-Id: Idec3d82efbdf095c3d57bfe5f0fd487007b554cb Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* cli_classic: add writeprotect CLI and update man pageNikolai Artemiev2022-04-212-5/+347
| | | | | | | | | | | | | | | | | Tested with: GD25LQ128, GD25Q32, GD25Q256. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=flashrom --wp-{enable,disable,range,region,list,status} Change-Id: I499f521781ee8999921996517802c0c0c641d869 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* raiden_debug_spi: Add more informative error message when WP is enabledRobert Zieba2022-04-211-0/+17
| | | | | | | | | | | | | | | | | | Current error messages are not very helpful when attempting to flash a target that has WP enabled. This change checks for the USB_SPI_DISABLED error that occurs in this case and gives a more informative error message. BUG=b:210645611 TEST=Tested with WP enabled and disable to verify that error message is displayed properly Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ib1e8383baa9c3ea41ab1079af12e3dc8cdff90ae Reviewed-on: https://review.coreboot.org/c/flashrom/+/62909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/: Add file path and flags validation to open() callsEdward O'Callaghan2022-04-182-20/+113
| | | | | | | | | | | | | | | | | With this change we add path and flag validation to many tests that do not call open. Expected path is set to NULL, if the code indead calls open then the assertion for non-NULL will make the test fail. BUG=b:217629892,b:215255210 TEST=`ninja test`. Change-Id: I892fa1ecee26ebce9640893edbb228fa9aa7b0b6 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Co-Author: Daniel Campello <campello@chromium.org> Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* raiden_debug_spi.c: Allow custom_rst param value of 'false'Edward O'Callaghan2022-04-151-2/+4
| | | | | | | | | | | | | | | As identified while documenting driver, allow for passing 'false' even though it is the default for custom_rst to be consistent. BUG=b:224358254 TEST=builds Change-Id: I25bfe6f8e3f7cfffb1a9c99ac90ec56a750d7f84 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-145-6/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* platform.h: rename swapX to ___swapXThomas Heijligen2022-04-141-6/+7
| | | | | | | | | | | OpenBSD has conflicting definitions for swapX and __swapX. Change-Id: I04d73967f694939c1127f48df8645a10e9dd66f3 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* hwaccess_x86_msr: drop outdated commentThomas Heijligen2022-04-131-1/+1
| | | | | | | | | Change-Id: Ia361f7f3392b4f58a33f3e2d3b5f8f4340c388b3 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* flashrom.c: remove unused includeThomas Heijligen2022-04-131-1/+0
| | | | | | | | | | | getopt.h is only needed in cli_classic.c Change-Id: I09b3233a128582bc98c5af77b6c89bd49984800e Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Drop STANDALONE modeThomas Heijligen2022-04-135-23/+2
| | | | | | | | | | | | | | | | STANDALONE mode was used to build flashrom without having support for file handling. This was relevant to build libflashrom on top of libpayload. For a while now, the code which is covered by STANDALONE has moved to cli_*.c and is not used for libflashrom. Therefore we can drop STANDALONE mode. Change-Id: I58fb82270a9884a323d9850176708d230fdc5165 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* NEED_PCI: remove macroThomas Heijligen2022-04-133-4/+0
| | | | | | | | | | The NEED_PCI macro is only used to guard prototypes. This is not needed. Change-Id: I6895b795bc96b3e251700bff4b0054407aac789a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* print_buildinfo: remove unreachable print of libpci versionThomas Heijligen2022-04-131-7/+0
| | | | | | | | | | | | | | | The libpci header is neither directly nor indirectly included in flashrom.c. `PCILIB_VERSION` is therefore never set and the following print statement is dead code. Since libpci is the only library in buildinfo, Drop it. Change-Id: I0b5dbf3bd82a2ffe64b73881383e92f7dad4c382 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* hwaccess_x86_msr: rename msr function to msr_xxxThomas Heijligen2022-04-134-61/+64
| | | | | | | | | | | | This eliminates the need to redefine the rdmsr and wrmsr symbols, resulting in more understandable code. The common prefix clarify the relation between the functions. Change-Id: Ie5ad54d198312578e0a1ee719eec67b37d2bf6a4 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* hwaccess: add endianness converting deserialization functionsThomas Heijligen2022-04-134-1/+58
| | | | | | | | | | | | | | | Add functions like `uint32_t read_le32(const void *base, size_t offset);` Read a 32 bit unsigned from a base with an offset. Having prototypes and a macro generated implementation makes it easier to read, understand and spot errors in one of them. Change-Id: Idde177acf8bc5f94cd046b6539dc31532c98e452 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/31016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* platform.h: remove const from forward declarationsThomas Heijligen2022-04-131-16/+16
| | | | | | | | | | | A `const` on the parameter itself is irrelevant to the caller. Change-Id: Iea26d75719ebb718203dbba883ac88f459c68c0a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63585 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/lifecycle.c: Deduce out io-setup-teardown do-patternEdward O'Callaghan2022-04-121-33/+19
| | | | | | | | | | | | | | | | | | | | | | | The following do-block is quite error prone to do manually, ``` io_mock_register(&XXX_io); run_probe_lifecycle(state, &XXX, "", ".."); io_mock_register(NULL); ```. Hence, deduce out the common pattern and fold up into the common worker function to handle state machine setup and teardown in a consistent way. BUG=b:227521116 TEST=`ninja test`. Change-Id: Icc00acd980a027337acb079f5afc3cccdfe4c765 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Daniel Campello <campello@chromium.org>
* sb600spi.c: Add Promontory chipset rev 0x71Karthikeyan Ramasubramanian2022-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | Sabrina SoC uses SMBUS revision code 0x71 which behaves exactly as the promontory chip. Hence add 0x71 as promontory. BUG=b:228238107 TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able to detect the SPI ROM chip, read from it and write to it successfully. Ran flashrom_tester on Skyrim (Sabrina SoC) successfully and ensured that all the tests passed. Change-Id: I2408959fbf1c105508f0a12f38418c9606280ab9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Endian conversion: move to platform.h and platform/endian*.cThomas Heijligen2022-04-126-11/+12
| | | | | | | | | | | Starting to move the platform dependent code to platform/ and provide the abstraction through the platform.h header. Change-Id: I35640282d451960f2a329ae24339ec05dbae6d30 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* hwaccess: replace macros by C codeThomas Heijligen2022-04-125-69/+167
| | | | | | | | | | | | | | Split the code for endian conversion into separate files for big and little endian. The buildsystem selects the correct file for the used endianness. Replace the swab macros with `static inline` c functions. Define macros for returning the same or swapped value. Call those macros in the endian specific files. Change-Id: I86d38d816b37c283279c485fac8027f8fb94364a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb600spi.c: Use SPI100 bit mappingsKarthikeyan Ramasubramanian2022-04-121-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On AMD SoCs that use SPI100 engine, flashrom has been using legacy spi100 register and bit mappings when programming the engine - specifically when programming the opcode and triggering their execution. --------------------------------------------------------------------- | Register Name | Legacy SPI100 mapping | Updated SPI100 mapping | |---------------|------------------------|--------------------------| | Opcode | Offset 0 from SPI BAR | Offset 0x45 from SPI BAR | | | Bits 0:7 | Bits 0:7 | |---------------|------------------------|--------------------------| | Execute Cmd | Offset 2 from SPI BAR | Offset 0x47 from SPI BAR | | | Bit 1 | Bit 7 | --------------------------------------------------------------------- These legacy register mappings are removed in upcoming generations of AMD SoCs. Stop using the legacy spi100 registers. For more details about SPI100 refer to document: 56569-A1 Rev 3.01 BUG=b:228238107 TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able to detect the SPI ROM chip, read from it and write to it successfully. Ran flashrom_tester on Dewatt (Cezanne SoC), Dalboz (Picasso SoC) successfully and ensured that all the tests passed. Change-Id: If42130757331f4294b5a42c848557d3287f24fc3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ich_descriptors.c: Ensure unsigned types >=0 on to prevent underflowaarya2022-04-111-4/+5
| | | | | | | | | | | | Unsigned types show undefined behaviour if they are subtracted by a value greater than their own (mostly it wraps to the max value). Using this value for left shifting could be even more dangerous. Change-Id: I5921cc571f3dca5188ca1973dba6ececbcbe2f39 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/linux_spi: Validate params file path and flagsEdward O'Callaghan2022-04-101-0/+6
| | | | | | | | | | | | | | | Add path and flags validation for '/dev/null' to open operation. BUG=b:217629892,b:215255210 TEST=`ninja test`. Signed-off-by: Edward O'Callaghan <quasisec@google.com> Co-Author: Daniel Campello <campello@chromium.org> Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: If5d24c65f291c53a35509fea5d2f5b3fdb51c306 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62319 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* hwaccess_physmap: add missing DirectHW includeThomas Heijligen2022-04-101-0/+1
| | | | | | | | | | | | | | | For MACH / APPLE map_physical is defined in DirectHW.h TEST: run `make` compiles, linking fails due to missing directhw object in my setup, don't know how to fix this Change-Id: I0e0f3fd587ae46e6f73418f2c83641cb1202478c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* README: add C compiler and pkg-config as build dependencyThomas Heijligen2022-04-071-0/+3
| | | | | | | | Change-Id: I64874dee905d8620f74acee98e0c8a149b067745 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62836 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: assert pathname and flags when calling open()Daniel Campello2022-04-064-16/+47
| | | | | | | | | | | | | | | | | | | With this change the wrappers for mock and friends are able to take an optional io_mock_fallback_open_state struct to assert expected pathnames and flags whenever an open operation is called. Based partially on https://review.coreboot.org/c/flashrom/+/62319/5 BUG=b:227404721,b:217629892,b:215255210 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Co-Author: Edward O'Callaghan <quasisec@google.com> Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb Reviewed-on: https://review.coreboot.org/c/flashrom/+/63227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: use MOCK_FD instead of NON_ZERODaniel Campello2022-04-063-9/+9
| | | | | | | | | | | | | | | | | | With this change the mocks are able to return a non-negative value for the file descriptor expected from open operations. This avoid issues with subsequent error checks of the form `if (fd < 0)` BUG=b:227404721 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect.c: refactor and fix wp_mode functionsNikolai Artemiev2022-04-051-10/+14
| | | | | | | | | | | | | | | | | | | | This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07. Use a lookup table in get_wp_mode() and drop the srp_bit_present check, since a chip without SRP is just FLASHROM_WP_MODE_DISABLED. Add a srp_bit_present check to set_wp_mode() if the mode requires it. BUG=b:182223106 BRANCH=none TEST=flashrom --wp-{enable,disable,status} on AMD dut Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libflashrom,linux_mtd: add linux_mtd writeprotect supportNikolai Artemiev2022-04-053-16/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a generic framework to allow opaque programmers to implement writeprotect operations and uses the framework to support writeprotect operations on linux MTD device files. The generic framework comprises three new functions in `struct opaque_master` that are called from libflashrom: - wp_write_cfg() - wp_read_cfg() - wp_get_ranges() For linux_mtd, only the read/write functions are implemented. Linux's MTD interface doesn't provide a way to get available ranges, so calling get_wp_ranges() on the linux_mtd master will return FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE. BUG=b:182223106 BRANCH=none TEST=WP ops on hana DUT (MT8173) with W25Q32DW flash TEST=flashrom --wp-enable --wp-range <non-empty> succeeds TEST=flashrom --wp-enable --wp-range <empty> fails as expected TEST=flashrom --wp-disable --wp-range <empty> succeeds TEST=flashrom --wp-disable --wp-range <non-empty> fails as expected TEST=flashrom --wp-status succeeds Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: add writeprotect support for more chipsNikolai Artemiev2022-04-051-14/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chips I had available for testing were tested with all writeprotect commands and an FT232H adapter. Chips I wasn't able to test were just checked against the datasheets. Chips used for testing (including chips added in previous patches) are listed in the table below: Flashrom Chip name | Chip(s) tested ---------------------------------+---------------------------- AT25SL128A | EN25QH128 | GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG GD25LQ64(B) | GD25LQ64CWIG GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG GD25Q256D | GD25Q256DYIG GD25Q64(B) | GD25Q64CSIG W25Q128.JW.DTR | W25Q128.V..M | W25Q128.W | W25Q256JV_M | W25Q256.V | W25Q64.W | XM25QH128C | XM25QH256C | BUG=b:182223106 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dmi.c: Ensure g_has_dmi_support is default on shutdownEdward O'Callaghan2022-04-051-0/+1
| | | | | | | | | | | | | | | | Ensure the g_has_dmi_support variable has the default state of false after the life-time has expired. BUG=none TEST=builds Change-Id: I0674950304736e53d014117d287682a4f6349879 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dmi.c: Hide has_dmi_support global behind methodEdward O'Callaghan2022-04-053-5/+10
| | | | | | | | | | | | | | | | | This allows has_dmi_support to be become static local to just the scope of dmi.c BUG=none TEST=builds Change-Id: Ibded9714998ea6f2e5d4e0512fa7c6b105f9638a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* gitignore: add libflashrom.aThomas Heijligen2022-04-051-0/+1
| | | | | | | | | | Change-Id: I9258a1710780df5c6a7c864de246ebbe850d60fe Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* spi25_statusreg: delete spi_read_status_register()Nikolai Artemiev2022-04-055-46/+141
| | | | | | | | | | | | | | | | | | | | | | | Delete the spi_read_status_register() function because the generic spi_read_register() function can be used instead. This patch also converts all call sites over to spi_read_register(). A side effect is that error codes are now properly propagated and checked. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut. Read SR1/SR2 with --wp-status and activated various WP ranges that toggled bits in both SR1 and SR2. Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi25_statusreg: inline spi_write_register_flag()Nikolai Artemiev2022-04-051-70/+56
| | | | | | | | | | | | | | | | | | | | | | | | Creating the entire SPI command that should be sent to the chip in spi_write_register() is simpler than splitting it across two functions that have to pass multiple parameters between them. Additionally, having separate spi_write_register_flag() function provided little benefit, as it was only ever called from spi_write_register(). BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut. Read SR1/SR2 with --wp-status and activated various WP ranges that toggled bits in both SR1 and SR2. Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-305-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sam McNally <sammc@google.com>
* libflashrom.c: Fix unintialized value passed to functionaarya2022-03-301-1/+1
| | | | | | | | | | | | | | | | | In function flash_layout_read_from_ifd variable chip_layout remains uninitialized if prepare_flash_access returns false. This uninitialized variable (which contains a garbage value) is passed to flashrom_layout_release. Thus initialize it with NULL. For completeness, also initialize dump_layout with NULL. Change-Id: Iacbd7bf9cdf897cc2a732c1dc6568845a4ab804d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62725 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* board_enable.c: Remove unnecessary assignmentaarya2022-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | In function board_asus_p3b_f there were two consecutive lines which modified the value of variable b // Do something with b b=INB(0x80); b=INB(smbba); //Do something with b Since the value of b is not used after first assignment, remove the first assignment. Change-Id: I7458b416a69fd5e2aa300ca49d1352b6074ad0bc Tested-by: Keith Hui <buurin@gmail.com> Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom.8.tmpl: document lspcon_i2c_spiPeter Marheine2022-03-291-11/+22
| | | | | | | | | | | | | This programmer operates much the same as realtek_mst_i2c_spi, so the I2C options are moved to a new section describing both programmers and a short description is added for this programmer itself. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I9ccb9694fdea29e68f062cc049efc0204917a139 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashrom.8.tmpl: document realtek_mst_i2c_spiPeter Marheine2022-03-291-0/+45
| | | | | | | | | | | This programmer was undocumented. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashrom.8.tmpl: Clarify man entries for -w/-v/-xDaniel Campello2022-03-292-7/+13
| | | | | | | | | | | | | | | | This change adds follow up changes to the man page: - Explain (-) argument for -w/-v operations - Expand on region name handling of -x operation Also updates cli_classic.c to match with --help output. BUG=b:224364316 Change-Id: I0cba593da3926c8587027789f4e1e89a2329ca7f Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* pony_spi.c: Fix memory leak in function pony_init_spiaarya2022-03-251-0/+1
| | | | | | | | | | | | | | | The issue was found by running scan-build. Memory leak was caused as data variable wasn't deallocated in some error cases where the function returned without deallocating it. After making the change, the issue no longer appeared in scan-build. Change-Id: I7910db94f63693e7f131836d4963e88cfdbec301 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* pcidev: Move pci_dev_find() from internal to canonical placeEdward O'Callaghan2022-03-226-33/+32
| | | | | | | | | | | | | | | | | Also rename to `pcidev_find()` in fitting with pcidev.c helpers. BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: Ie21f87699481a84398ca4450b3f03548f0528191 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pcidev: Move pci_card_find() from internal to canonical placeEdward O'Callaghan2022-03-224-28/+27
| | | | | | | | | | | | | | | | | | | Also rename to `pcidev_card_find()` in fitting with pcidev.c helpers. BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: I026bfbecba114411728d4ad1ed8969b469fa7d2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Add padding to pci_dev struct for ASANDaniel Campello2022-03-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change addresses the following ASAN error detected in the chromium tree: * ASAN error detected: * ================================================================= * ==12==ERROR: AddressSanitizer: global-buffer-overflow on address 0x55a8a046c916 at pc 0x55a8a038a21d bp 0x7ffd5dbc9ed0 sp 0x7ffd5dbc9ec8 * READ of size 2 at 0x55a8a046c916 thread T0 * #0 0x55a8a038a21c in nicrealtek_init /build/amd64-generic/tmp/por tage/sys-apps/flashrom-9999/work/flashrom-9999-build/../flashrom-9999/ni crealtek.c:119:15 * #1 0x55a8a032f172 in __sanitizer::BufferedStackTrace::UnwindImpl( unsigned long, unsigned long, void*, bool, unsigned int) ??:0:0 * #2 0x55a8a02b65b8 in __asan::ErrorGeneric::Print() ??:0:0 * #3 0x55a8a03294d5 in __asan::ScopedInErrorReport::~ScopedInErrorR eport() ??:0:0 * #4 0x55a8a032c5ae in __asan::ReportGenericError(unsigned long, un signed long, unsigned long, unsigned long, bool, unsigned long, unsigned int, bool) ??:0:0 * #5 0x55a8a032d0f7 in __asan_report_load2 ??:0:0 * * 0x55a8a046c916 is located 18 bytes to the right of global variable 'm ock_pci_dev' defined in '../flashrom-9999/tests/tests.c:50:16' (0x55a8a0 46c900) of size 4 * SUMMARY: AddressSanitizer: global-buffer-overflow (/tmp/portage/sys-a pps/flashrom-9999/work/flashrom-9999-build/tests/flashrom_unit_tests+0x1 9a21c) * Shadow bytes around the buggy address: * 0x0ab5940858d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab5940858e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab5940858f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab594085900: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab594085910: 00 00 00 00 00 00 f9 f9 f9 f9 f9 f9 f9 f9 00 00 * =>0x0ab594085920: 04 f9[f9]f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085930: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085940: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085950: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085960: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085970: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * Shadow byte legend (one shadow byte represents 8 application bytes): * Addressable: 00 * Partially addressable: 01 02 03 04 05 06 07 * Heap left redzone: fa * Freed heap region: fd * Stack left redzone: f1 * Stack mid redzone: f2 * Stack right redzone: f3 * Stack after return: f5 * Stack use after scope: f8 * Global redzone: f9 * Global init order: f6 * Poisoned by user: f7 * Container overflow: fc * Array cookie: ac * Intra object redzone: bb * ASan internal: fe * Left alloca redzone: ca * Right alloca redzone: cb * ==12==ABORTING BUG=b:224828279 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I47943bf70181a9041f287df3ece0f7067a112de8 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62845 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* helpers.c: use unsigned int for bit shifts (ASAN)Daniel Campello2022-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This change addresses the following ASAN error detected in the chromium tree: * ASAN error detected: * ../flashrom-9999/helpers.c:28:13: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' * #0 0x5589a94bb284 in address_to_bits /build/amd64-generic/tmp/portage/sys-apps/flashrom-9999/work/flashrom-9999-build/../flashrom-9999/helpers.c:28:13 * * SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../flashrom-9999/helpers.c:28:13 in BUG=b:224828279 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: Ib595f13c29dd5c0775e074801756e4f920b4daaf Reviewed-on: https://review.coreboot.org/c/flashrom/+/62862 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: add more mock wrappersDaniel Campello2022-03-212-0/+27
| | | | | | | | | | | | | | | | | | | | | | | This change allows for tests to run when the compiler is inlining some other interfaces. This happens when compiling on the chromium chroot environment. * __fgets_chk() is being used instead of fgets() in get_max_kernel_buf_size() on linux_spi.c * __vfprintf_chk() is being used instead of fprintf() in disable_power_management() on power.c * __open64_2() is being used instead of open() in i2c_open_path() on i2c_helper_linux.c BUG=b:224828279 TEST=./test_build.sh; FEATURES=test emerge-volteer flashrom Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I9776104d655c37891093da08789d37e5e27700de Reviewed-on: https://review.coreboot.org/c/flashrom/+/62844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* cli_classic.c: Use correct format specifier for `size_t`Angel Pons2022-03-201-1/+1
| | | | | | | | | | | | The return value of `flashrom_flash_getsize()` is of `size_t` type. Fixes: commit 83c5c50f91806df599fa9eebb654832879381772 Change-Id: I8025c0e046cb61e0e115d3786e6e4184190347f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 15:26:49 +0000