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* spi: Make default cmd helpers static internalEdward O'Callaghan2023-03-032-23/+19
| | | | | | | | | | | | | | | | | | | | Avoid these leaking into driver implementations as a NULL field now implies their implementation. This removes one source of a driver bug where both `mst->command` AND `mst->multicommand` are set to default implementations which is actually a cyclical control flow condition. The driver however must still have either `mst->command` OR `mst->multicommand` defined and so both cannot be NULL. This simplifies the code and driver development. Change-Id: I4ef95846c2f005cf4aa727f31548c6877d2d4801 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect: Add function to get register values and WP bit masksNikolai Artemiev2023-03-035-0/+101
| | | | | | | | | | | | | | | | | | | | | | | Add a new wp_cfg_to_reg_values() function that takes a generic wp_cfg instance and returns the chip-specific values that need to be written to the chip's registers to enable the specified protection range/mode. The function returns three values for each chip register: - reg_values[reg] - Value writeprotect will write to reg - bit_masks[reg] - Bit mask for WP-related bits in reg - write_masks[reg] - Bit mask for writable WP-related bits in reg (i.e. the ones writeprotect will try to write) BUG=b:260019525,b:259013033,260020006 BRANCH=none TEST=ninja test Change-Id: Ib2a47153b230c9f82bb4eca357c335f2abbacc20 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69847 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* dummyflasher: Add basic WP support for opaque VARIABLE_SIZE chipNikolai Artemiev2023-03-021-0/+30
| | | | | | | | | | | | | | | | | | | | | | | Since VARIABLE_SIZE emulated chips do not correspond to actual flash chip models, no active protection modes are supported: - read_wp_cfg always returns mode=disabled,range=0,0 - write_wp_cfg only accepts mode=disabled,range=0,0 However this is sufficient to support use cases where the user just needs to verify that write protection is not enabled, as is the case in some futility unit tests. BUG=b:238694831,b:260531154 BRANCH=none TEST=none Change-Id: I4348e0175b8c743365904f5e61fdb69e3f4f4db5 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73289 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi: Make 'default_spi_send_multicommand' the default unless definedEdward O'Callaghan2023-03-0125-30/+5
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_send_multicommand' as to not need this explicit specification of 'default'. Therefore drop the explicit need to specify the 'default_spi_send_multicommand' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I6cc24bf982da3d5251d391eb397db43dd10280e8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* doc/classic_cli_manpage: add missing chip for ft2232_spi programmerAlexander Goncharov2023-03-011-1/+1
| | | | | | | | | | | FTDI FT4233H chip was added in commit bc2e3b6b79dd1383cdf3d965df2fc5c0d6596b02 Change-Id: Id25f6444bfe871f7b01ae2caff23ce973b44567a Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* move manpage to sphinxThomas Heijligen2023-03-019-1870/+1468
| | | | | | | | | | | | | | | | | | | | | | | | | Use sphinx (sphinx-doc.org) to generate the UNIX man page from an reStructuredText file instead of dealing with plain groff. Use `meson setup -Dman-pages=enabled` to build the man page, and `meson setup -Ddocumentation=enabled` to build the web documentation explicitly. Both are enabled automatically if sphinx-build is found. The man page will be installed as `<meson_mandir>/man8/flashrom.8` and The html documentation in <meson_datadir>/doc/flashrom/html`. The Makefile builds only the man-page format. Increase the minimum version of meson from 0.53.0 to 0.57.0 to be able to pass environment variables to the custom_target() command. That is needed to pass the FLASHROM_VERSION to the documentation. Change-Id: Iee9f1164c5913e47385e6f7d51dc7775a58b5a67 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* spi: Make 'default_spi_send_command' the default unless definedEdward O'Callaghan2023-02-272-5/+5
| | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_send_command' as to not need this explicit specification of 'default'. Therefore drop the explicit need to specify the 'default_spi_send_command' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I63abcb8c64f233cdbf58a149a31051fa648305a2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Provide better lexical scope to itermediatesEdward O'Callaghan2023-02-271-10/+6
| | | | | | | | | Change-Id: I8e01d471bb33a933b80760df2c69a4bf3589ba76 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Tidy up whitespace and line wrapsEdward O'Callaghan2023-02-271-7/+6
| | | | | | | | | Change-Id: I3f18609709e59cdfc5a853c6e1ae5f53aecacc1a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Add a little more const correctnessEdward O'Callaghan2023-02-271-5/+4
| | | | | | | | | Change-Id: Ic9a76ce3734bd83399c95478a7c0bfc081211124 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Rename func to jedec_write_page()Edward O'Callaghan2023-02-271-2/+2
| | | | | | | | | Change-Id: I1be83d5974e305bddceaa34b64e982b774ade0d2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Drop branching non-zero programmer_delay() operandsEdward O'Callaghan2023-02-271-10/+5
| | | | | | | | | | | | | The programmer_delay() function is already tolerant upon zero delay values and will simply just return with a NOP. Therefore there is no need to branch. Change-Id: Ic547669bb16e6ace4fe283e07345fc2d7075d63e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ch347_spi: Add initial support for the WCH CH347Nicholas Chin2023-02-279-10/+386
| | | | | | | | | | | | | | | | | | | | | | | Add support for the WCH CH347, a high-speed USB to bus converter supporting multiple protocols interfaces including SPI. Currently only mode 1 (vendor defined communication interface) is supported, mode 2 (USB HID communication interface) support will be added later. The code is currently hard coded to use CS1 and a SPI clock of 15 MHz, though there are 2 CS lines and 6 other GPIO lines available, as well as a configurable clock divisor for up to 60MHz operation. Support for these will be exposed through programmer parameters in later commits. This currently uses the synchronous libusb API. Performance seems to be alright so far, if it becomes an issue I may switch to the asynchronous API. Tested with a MX25L1606E flash chip Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Reviewed-on: https://review.coreboot.org/c/flashrom/+/70573 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* asm106x: add programmer for ASM106x SATA controllersAlex Badea2023-02-278-9/+190
| | | | | | | | | | | | | | | | | | | | The ASMedia ASM106x series is a PCIe-SATA controller chip. It supports an attached SPI flash chip that can contain configuration and PCI option ROM. The interface is a simple shifter accessed via PCI config space, up to 4 bytes at a time. Add a programmer driver for it. Tested on a G536PCE1061V11 IO-PCE1061-V1.1 PCIe card, and a MPCE2ST-A01 VER006S mini-PCIe card, both with chips marked ASM1061, both enumerate as: 01:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:1060] Change-Id: I591b117be911bdb8249247c20530c1cf70f6e70d Signed-off-by: Alex Badea <vamposdecampos@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* MAINTAINERS: Update unit tests from Supported to MaintainedAnastasia Klimchuk2023-02-271-1/+1
| | | | | | | | Change-Id: I13853c6c48eb4054d2ed7d79bcfc768684914797 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73277 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: flashrom_tester: Change emailEvan Benn2023-02-261-1/+1
| | | | | | | | | | Change-Id: Ic1a53ddbc38e7d63f7b15aa2b31c63a5b65746f9 Signed-off-by: Evan Benn <evanbenn@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* erasure_layout.c: Test erasefn_count before using it to allocate memoryThomas Heijligen2023-02-231-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In erasure_layout.c:create_erase_layout() the layout will be allocated based on erasefn_count, But calling calloc with 0 is unspecified behavior. Also it is not freed when erasefn_count is 0. So test first if erasefn_count is 0, and only when not allocate the memory for *layout. Reported by Coverty Scan: *** CID 1505171: Resource leaks (RESOURCE_LEAK) /erasure_layout.c: 105 in create_erase_layout() 98 if(!layout) { 99 msg_gerr("Out of memory!\n"); 100 return -1; 101 } 102 103 if (!erasefn_count) { 104 msg_gerr("No erase functions supported\n"); >>> CID 1505171: Resource leaks (RESOURCE_LEAK) >>> Variable "layout" going out of scope leaks the storage it points to. 105 return 0; 106 } Change-Id: If13b050ac8525fee44d3f3bf74a9c9b6a8d38399 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* jedec.c: Move probe_timings decode into sep funcEdward O'Callaghan2023-02-221-11/+19
| | | | | | | | | | | | The chip data structure packed from the flashchips db should have the probe_timing field decoded by its own function. Change-Id: I638518cd537954172eb774f6d15af0db7e06d1ba Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72609 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Fold up mask param into funcEdward O'Callaghan2023-02-211-9/+8
| | | | | | | | Change-Id: Iee4b1d5bc850cbeec0de9a1603fe04a3a1855330 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72631 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Rewrite control flow procedurallyEdward O'Callaghan2023-02-211-35/+33
| | | | | | | | | | Drop goto usage in fav of loop constructs. Change-Id: I0927ed40e54cc7e114a57dc40e3614f4825a0ca9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72608 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Move printlock stuff into printlock.cEdward O'Callaghan2023-02-214-190/+215
| | | | | | | | | Change-Id: Iacaa16c81e141aac30feb6871700c4fdc9eec8e9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72607 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Add reg_bits for W25Q256JW_DTRKapil Porwal2023-02-211-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add reg_bits for W25Q256JW_DTR as per the datasheet. BUG=b:263410331 TEST=Verified on google/rex. w/o this patch: Failed to get WP status: WP operations are not implemented for this chip w/ this patch: flashrom -p internal --wp-range 0x0,0x2000000 flashrom -p internal --wp-enable flashrom -p internal --wp-status flashrom -p internal -E <---- failed to erase the flash as WP (which is expected) Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Fold up dst into toggle_ready_jedec()Edward O'Callaghan2023-02-211-10/+5
| | | | | | | | | Change-Id: Ib7a3fdbc6e0a888093dc8da6f5567a7301ec5040 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* dummyflasher: use new API to register shutdown functionAlexander Goncharov2023-02-201-15/+26
| | | | | | | | | | | | | | | | | | | | | This allows masters to register shutdown function in *_master struct, which means there is no need to call register_shutdown in init function, since this call is now a part of register_*_master. A dummy programmer can register masters for multiple buses that share a programmer's data (a pointer to struct emu_data) with each other. To avoid unexpected memory freeing by shutdown function, we need to keep track of how many buses are using the shared resource. Use the reference counting technique to achieve this. TEST=ninja test Change-Id: I0c67c25b0f53cd8c564c4ea0f09f2728e856f6ea Signed-off-by: Alexander Goncharov <chat@joursoir.net> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/72408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Trivial code style fixEdward O'Callaghan2023-02-171-2/+1
| | | | | | | | Change-Id: Iacdb62067a8d22261d4eabe73ad96168eb11417c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* cli_classic.c: Drop spurious castEdward O'Callaghan2023-02-171-2/+1
| | | | | | | | | | This cast should not be required. Change-Id: Ia3a658dd6f4986eb6da84a11bce66f53e1571469 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* jedec.c: Consolidate op,operand sequencing into funcEdward O'Callaghan2023-02-161-52/+19
| | | | | | | | Change-Id: I9a1b211b49777f6d7f62a052975c1759e036c8df Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72502 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* serial: Add Darwin/macOS support for custom and >230400 baudratesPeter Stuge2023-02-164-0/+71
| | | | | | | | | | | This change is based on the patch proposed by Denis Ahrens in https://review.coreboot.org/c/flashrom/+/67822 Change-Id: I3e6b88d2b4c2a130b16456752681fd9f807bf6f0 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* serial: Call set_custom_baudrate() thricePeter Stuge2023-02-164-6/+27
| | | | | | | | | | | | | | | | | | | | | | | Call the function before tcsetattr() settings are known, then again with settings prepared but not yet applied and finally a third time after tcsetattr(). Darwin support needs this change; there custom_baud code must be called to modify the settings passed to tcsetattr() and then again after tcsetattr() returns. The change should be non-functional on all currently supported systems; current code calls set_custom_baudrate() before any tcsetattr() settings are prepared, so we have three stages in total. This change originates from discussion of the macOS patch proposed by Denis Ahrens in https://review.coreboot.org/c/flashrom/+/67822 Change-Id: I40cc443cfb7bf6b212b31826d437b898cc13c427 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* meson: Determine custom_baud source file only oncePeter Stuge2023-02-161-3/+9
| | | | | | | | | Change-Id: I13221bdca7d14a483f416e81e3830a495659a85e Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* Add missing Intel B460 flash chip idChristopher Lentocha2023-02-161-0/+1
| | | | | | | | | | | | | | | | | Note that while I can read the chip, on my Lenovo Legion T5 28IMB05, cannot write to the flash chip with any tools except upgrading with vendor tool, no downgrades are allowed, due to the fact of SMM, even if I did manage to flash the BIOS chip somehow, would still face bootguard since this machine has bootguard. But if I read the chip, and verify my read bin file, it works fine, until changing the SMBIOS, which is in the vendor BIOS update package. Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Signed-off-by: Christopher Lentocha <christopherericlentocha@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72056 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal: Move parallel logic into internal_par implementationEdward O'Callaghan2023-02-155-60/+87
| | | | | | | | | | | | | The parallel internal programmer is its own implementation. Move it and call into it from the top-level internal.c programmer implementation. Change-Id: Idabeceb59a36680f5fbb45d3ee4bd5dbf837373b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71834 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal.c: Factor out laptop alerts into helper funcEdward O'Callaghan2023-02-141-25/+31
| | | | | | | | | | | | | Minor however a unfortunate '_' suffix is temporarily needed to skirt around global variable shadowing. Change-Id: I8eea91012e6539b4fdf5d49a75a9cb48bb8a57ca Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: Add new erase_by_layout and walk_by_layout implementationsAarya Chaumal2023-02-131-2/+81
| | | | | | | | | | | | Add [erase,walk]_by_layout_new to use optimised implementations of the erase function selection algorithm. Change-Id: Id79ae943eb9d6a817da28381db477725834faaf6 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71173 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom.c: Add functions for new erase selection algorithmAarya Chaumal2023-02-134-1/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add function to flatten out the addresses of the flash chip as per the different erase functions. This function will return a list of layouts which is dynamically allocated. So after use all the layouts as well as the list itself should be freed. The free_erase_layout function does that. 2) Add function to align start and end address of the region (in struct walk_info) to some erase sector boundaries and modify the region start and end addresses to match nearest erase sector boundaries. This function will be used in the new algorithm for erase function selection. 3) Add function that returns a list of sectors (as seen by the first erase function) that need erasing. 4) Add a function to call the erase algorithm. Change-Id: Ic57ca1cca3d1646543f6b5939ba9c35db8d08256 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom.c: Add switch for legacy impl of erasure pathEdward O'Callaghan2023-02-131-2/+20
| | | | | | | | | | | | | | | As part of a GSoC project to optimise the erasure path in flashrom a completely different algorithm is used to perform erasure. Therefore we need a mechanism to have the two implementations side by side to allow for A/B testing and easy reverts should issue arise. Change-Id: Ib5660db0067c1c799dcb5c8e83b4a4826b236442 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71119 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tests: add bus coverage test for dummyAlexander Goncharov2023-02-093-0/+21
| | | | | | | | | | | | | | | Dummy programmer has a shared data between *_masters. To make sure the dummy has no memory leakage, we need a test that will covers initialization and shutdown of the programmer with different bus types, i.e. programmer specific, non-SPI and SPI. TEST=ninja test Change-Id: Iafe715feb5f5c0b5efd6827cdb2c3a314f542319 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom_tester: Add positive check to verify_fail_testEvan Benn2023-02-064-2/+50
| | | | | | | | | | | | | | | | | In verify_fail_test test that verify works when expected, as well as fails when expected. A verify_region_from_file function is added to support this. BUG=b:235916336 BRANCH=None TEST=None Change-Id: Ibbcc97086466b67cfab4f6c32140bb5f2c456beb Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71974 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Rewrite IOOpts to support more operationsEvan Benn2023-02-064-134/+133
| | | | | | | | | | | | | | | | | | flashrom cli supports include regions for all of read write and verify, as well as omitting the read/write/verify file if an include region with file is specified. Use an enum to allow only one operation at a time. Unify the read and write region implementations. BUG=b:235916336 BRANCH=None TEST=None Change-Id: I1cb46bb1b26949fd9c19949c43708a8b652e00da Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Rename lock_test hwwp_locks_swwp_testEvan Benn2023-02-061-2/+2
| | | | | | | | | | | | | | | Rename lock_test to hwwp_locks_swwp_test. BUG=b:235916336 BRANCH=None TEST=None Change-Id: I6080622755ff16d8fba7044b38f9e09db0c62f97 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* internal.c: Move sio register to own objectEdward O'Callaghan2023-02-044-29/+44
| | | | | | | | | | | | | | While super i/o is related to the internal programmer it isn't actually _the_ internal programmer. Move register logic to its own object consistent with other programmer types. Change-Id: I9a4c3e12bce5d22492c8d1b8f4a3f49d736dcf31 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71577 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Trivial code style fixEdward O'Callaghan2023-02-021-4/+2
| | | | | | | | Change-Id: I42ebdda07512d0a84a6bd6d0630f96c40f039259 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72606 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse probe_jedec() indirectionEdward O'Callaghan2023-02-021-9/+4
| | | | | | | | Change-Id: I57c27bcf25c5d9ce10fb9c74d9be6ab3544ac7ba Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72504 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse erase_chip_block_jedec() indirectionEdward O'Callaghan2023-02-021-16/+11
| | | | | | | | Change-Id: I6e4a63e4935d4b69b66cbd1888f62b6af066a2ac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72503 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse erase_block_jedec() indirectionEdward O'Callaghan2023-02-021-9/+2
| | | | | | | | Change-Id: Ia9b539d7fb4a54ba6cc56730e96d35044e291844 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72501 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse erase_sector_jedec() indirectionEdward O'Callaghan2023-02-021-9/+2
| | | | | | | | Change-Id: I9cc9e8c88c0442dc2602bbb2de2073113e9c484b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72500 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Make getaddrmask() ret const correctEdward O'Callaghan2023-02-021-19/+7
| | | | | | | | Change-Id: If9701a6d56159d0dfc047aa91b2a80c80fb33e5f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72499 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher.c: Speed up programmer ops without delayEdward O'Callaghan2023-02-011-0/+7
| | | | | | | | | | | | | | | | There is no need to perform delays for the dummyflasher as there is no chipsets to settle down. BUG=b:266014935 TEST=builds Change-Id: I43411b6d1558d1a5da4c7508618f8a6ec6d9bf95 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72423 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmers: Allow opaque programmers to specify custom delayEdward O'Callaghan2023-02-012-0/+4
| | | | | | | | | | | | | | | The dummyprogrammer in the opaque case can have a NOP delay to avoid wasting CPU time and energy. BUG=b:266014935 TEST=builds Change-Id: Ia86ad21f011214abc2aa0891a43559f91e2a9591 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72424 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom_tester: Simplify wp_toggle_test and renameEvan Benn2023-01-311-5/+2
| | | | | | | | | | | | | | | | | Rename wp_toggle_test to wp_region_list_test. Make it test one thing, wp_list. lock_test does the test of set_hw/set_sw functionality so that was redundant here. BUG=b:235916336 BRANCH=None TEST=None Change-Id: I314aa8d9708c39cc162a8d5e95ca3e019c2fb5b8 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-08 23:14:47 +0000