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* Add missing Intel B460 flash chip idChristopher Lentocha2023-02-161-0/+1
* chipset_enable.c: add PCI ID for TGL-UP3Jan Samek2023-01-181-0/+1
* tree/: Rename ERROR_NONFATAL to ERROR_FLASHROM_NONFATALEdward O'Callaghan2022-11-091-9/+9
* tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATALEdward O'Callaghan2022-11-091-24/+24
* chipset_enable.c: Mark Intel C246 as DEPAngel Pons2022-10-311-1/+1
* tree: Retype variable `laptop_ok` with boolFelix Singer2022-09-081-4/+4
* tree: Retype variable `programmer_may_write` with boolFelix Singer2022-09-081-1/+2
* chipset_enable.c: plumb programmer_cfg into sb600 and ich initEdward O'Callaghan2022-09-071-5/+5
* tree: plumb programmer_cfg into chipset_flash_enable()Edward O'Callaghan2022-09-071-2/+2
* ichspi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-3/+3
* chipset_enable.c: Change doit() and enable_flash_\S() signaturesEdward O'Callaghan2022-09-071-111/+111
* tree: Port programmers to pass programmer_cfg to extractorsEdward O'Callaghan2022-09-071-1/+1
* sb600spi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-1/+1
* tree: Change signature of extract_programmer_param_str()Edward O'Callaghan2022-09-071-1/+1
* Add `str` extension to extract_programmer_param function nameChinmay Lonkar2022-07-021-1/+1
* ichspi: Add Intel Alder Lake-S supportMichał Kopeć2022-05-191-0/+9
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-141-0/+9
* hwaccess_x86_msr: rename msr function to msr_xxxThomas Heijligen2022-04-131-6/+6
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-301-0/+9
* pcidev: Move pci_dev_find() from internal to canonical placeEdward O'Callaghan2022-03-221-3/+3
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-071-0/+10
* pcidev: Move scandev_inclass logic from internal to pcidevEdward O'Callaghan2022-03-041-3/+3
* Add Elkhart Lake supportWerner Zeh2022-02-041-0/+9
* hwaccess: fix build on non-x86 targetsPeter Marheine2022-01-251-2/+3
* hwaccess: move mmio functions into hwaccess_physmapThomas Heijligen2022-01-201-1/+0
* chipset_enable.c: Add TGP-H IDsTim Crawford2022-01-051-0/+9
* physmap: rename to hwaccess_physmap, create own headerThomas Heijligen2021-12-221-0/+1
* hwaccess physmap: move x86 msr related code into own filesThomas Heijligen2021-12-221-0/+1
* hwaccess: move x86 port I/O related code into own filesThomas Heijligen2021-12-221-0/+1
* pci.h: move include into own wrapperThomas Heijligen2021-12-221-0/+1
* chipset_enable.c: Mark Intel Z390 as DEPmelvyn22021-11-171-1/+1
* Add Tiger Lake U Premium supportMichał Żygowski2021-11-171-0/+14
* chipset_enable.c: Mark Z97 as DEPSophie van Soest2021-09-131-1/+1
* Add support for Intel Emmitsburg PCHJonathan Zhang2021-09-011-0/+1
* chipset_enable.c: Add Gemini Lake eSPI PCI device IDAngel Pons2021-05-181-0/+1
* Add Gemini Lake supportAngel Pons2021-05-161-0/+9
* chipset_enable.c: Add IDs for H310C and B365 PCHsAngel Pons2021-04-271-0/+2
* chipset_enable.c: Add CMP-H IDsGaggery Tsai2021-04-261-0/+7
* chipset_enable: Mark QS67 as DEPEvgeny Zinoviev2021-04-241-1/+1
* chipset_enable.c: Add PCI ID for Comet Lake U BaseSam McNally2021-03-111-0/+1
* chipset_enable: Mark Intel C216 as DEPJacob Garber2021-02-281-1/+1
* chipset_enable.c: Mark Intel H110 as DEPAngel Pons2020-12-181-1/+1
* chipset_enable.c: mark "Broadwell U Base" as DEPNikolai Artemiev2020-12-141-1/+1
* chipset_enable.c: Validate physmap() return rcrb valueEdward O'Callaghan2020-12-021-0/+2
* chipset_enable.c: Mark Intel Q67 as DEPAngel Pons2020-11-231-1/+1
* chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} supportEdward O'Callaghan2020-11-141-0/+3
* chipset_enable.c: check return value from rphysmap() callEdward O'Callaghan2020-10-271-0/+2
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-0/+9
* chipset_enable: Mark Intel Q77 as DEPJacob Garber2020-08-291-1/+1
* add PCI IDs for additional c620 series PCH chipsJonathan Zhang2020-08-271-0/+3
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