1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
|
/*
* This file is part of the flashrom project.
*
* Copyright (C) 2010 Carl-Daniel Hailfinger
* Copyright (C) 2010 Idwer Vollering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Datasheets:
* PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
* 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
* http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x-family-gbe-controllers-software-dev-manual.html
*
* PCIe GbE Controllers Open Source Software Developer's Manual
* http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe-controllers-open-source-manual.html
*
* Intel 82574 Gigabit Ethernet Controller Family Datasheet
* http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-controller-datasheet.html
*
* Intel 82599 10 GbE Controller Datasheet (331520)
* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82599-10-gbe-controller-datasheet.pdf
*/
#include <stdlib.h>
#include <unistd.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess.h"
#define PCI_VENDOR_ID_INTEL 0x8086
#define MEMMAP_SIZE getpagesize()
/* EEPROM/Flash Control & Data Register */
#define EECD 0x10
/* Flash Access Register */
#define FLA 0x1c
/*
* Register bits of EECD.
* Table 13-6
*
* Bit 04, 05: FWE (Flash Write Enable Control)
* 00b = not allowed (on some cards this sends an erase command if bit 31 (FL_ER) of FLA is set)
* 01b = flash writes disabled
* 10b = flash writes enabled
* 11b = not allowed
*/
#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
/* Flash Access register bits
* Table 13-9
*/
#define FL_SCK 0
#define FL_CS 1
#define FL_SI 2
#define FL_SO 3
#define FL_REQ 4
#define FL_GNT 5
#define FL_LOCKED 6
#define FL_ABORT 7
#define FL_CLR_ERR 8
/* Currently unused */
// #define FL_BUSY 30
// #define FL_ER 31
#define BIT(x) (1<<(x))
static uint8_t *nicintel_spibar;
const struct dev_entry nics_intel_spi[] = {
{PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x10d8, NT, "Intel", "82599 10 Gigabit Unprogrammed Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "82599 10 Gigabit KX4 Dual Port Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller"},
{PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit CX4 Dual Port Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599 10-Gigabit SFI/SFP+ Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit XAUI/BX4 Dual Port Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x1517, NT, "Intel", "82599 10 Gigabit KR Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x151c, NT, "Intel", "82599 10 Gigabit TN Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x1529, NT, "Intel", "82599 10 Gigabit Dual Port Network Controller with FCoE"},
{PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"},
{PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"},
{PCI_VENDOR_ID_INTEL, 0x1531, OK, "Intel", "I210 Gigabit Network Connection Unprogrammed"},
{PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"},
{PCI_VENDOR_ID_INTEL, 0x1533, NT, "Intel", "I210 Gigabit Network Connection"},
{PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"},
{PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"},
{PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"},
{PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"},
{0},
};
static void nicintel_request_spibus(void)
{
uint32_t tmp;
tmp = pci_mmio_readl(nicintel_spibar + FLA);
tmp |= BIT(FL_REQ);
pci_mmio_writel(tmp, nicintel_spibar + FLA);
/* Wait until we are allowed to use the SPI bus. */
while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ;
}
static void nicintel_release_spibus(void)
{
uint32_t tmp;
tmp = pci_mmio_readl(nicintel_spibar + FLA);
tmp &= ~BIT(FL_REQ);
pci_mmio_writel(tmp, nicintel_spibar + FLA);
}
static void nicintel_bitbang_set_cs(int val)
{
uint32_t tmp;
tmp = pci_mmio_readl(nicintel_spibar + FLA);
tmp &= ~BIT(FL_CS);
tmp |= (val << FL_CS);
pci_mmio_writel(tmp, nicintel_spibar + FLA);
}
static void nicintel_bitbang_set_sck(int val)
{
uint32_t tmp;
tmp = pci_mmio_readl(nicintel_spibar + FLA);
tmp &= ~BIT(FL_SCK);
tmp |= (val << FL_SCK);
pci_mmio_writel(tmp, nicintel_spibar + FLA);
}
static void nicintel_bitbang_set_mosi(int val)
{
uint32_t tmp;
tmp = pci_mmio_readl(nicintel_spibar + FLA);
tmp &= ~BIT(FL_SI);
tmp |= (val << FL_SI);
pci_mmio_writel(tmp, nicintel_spibar + FLA);
}
static int nicintel_bitbang_get_miso(void)
{
uint32_t tmp;
tmp = pci_mmio_readl(nicintel_spibar + FLA);
tmp = (tmp >> FL_SO) & 0x1;
return tmp;
}
static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
.set_cs = nicintel_bitbang_set_cs,
.set_sck = nicintel_bitbang_set_sck,
.set_mosi = nicintel_bitbang_set_mosi,
.get_miso = nicintel_bitbang_get_miso,
.request_bus = nicintel_request_spibus,
.release_bus = nicintel_release_spibus,
.half_period = 1,
};
static int nicintel_spi_shutdown(void *data)
{
uint32_t tmp;
/* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */
tmp = pci_mmio_readl(nicintel_spibar + EECD);
tmp &= ~FLASH_WRITES_ENABLED;
tmp |= FLASH_WRITES_DISABLED;
pci_mmio_writel(tmp, nicintel_spibar + EECD);
return 0;
}
static int nicintel_spi_82599_enable_flash(void)
{
uint32_t tmp;
/* Automatic restore of EECD on shutdown is not possible because EECD
* does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,
* but other bits with side effects as well. Those other bits must be
* left untouched.
*/
tmp = pci_mmio_readl(nicintel_spibar + EECD);
tmp &= ~FLASH_WRITES_DISABLED;
tmp |= FLASH_WRITES_ENABLED;
pci_mmio_writel(tmp, nicintel_spibar + EECD);
/* test if FWE is really set to allow writes */
tmp = pci_mmio_readl(nicintel_spibar + EECD);
if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
msg_perr("Enabling flash write access failed.\n");
return 1;
}
if (register_shutdown(nicintel_spi_shutdown, NULL))
return 1;
return 0;
}
static int nicintel_spi_i210_enable_flash(void)
{
uint32_t tmp;
tmp = pci_mmio_readl(nicintel_spibar + FLA);
if (tmp & BIT(FL_LOCKED)) {
msg_perr("Flash is in Secure Mode. Abort.\n");
return 1;
}
if (!(tmp & BIT(FL_ABORT)))
return 0;
tmp |= BIT(FL_CLR_ERR);
pci_mmio_writel(tmp, nicintel_spibar + FLA);
tmp = pci_mmio_readl(nicintel_spibar + FLA);
if (!(tmp & BIT(FL_ABORT))) {
msg_perr("Unable to clear Flash Access Error. Abort\n");
return 1;
}
return 0;
}
int nicintel_spi_init(void)
{
struct pci_dev *dev = NULL;
if (rget_io_perms())
return 1;
dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0);
if (!dev)
return 1;
uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
if ((dev->device_id & 0xfff0) == 0x1530) {
nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000,
MEMMAP_SIZE);
if (!nicintel_spibar || nicintel_spi_i210_enable_flash())
return 1;
} else if (dev->device_id < 0x10d8) {
nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr,
MEMMAP_SIZE);
if (!nicintel_spibar || nicintel_spi_82599_enable_flash())
return 1;
} else {
nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000,
MEMMAP_SIZE);
if (!nicintel_spibar || nicintel_spi_82599_enable_flash())
return 1;
}
if (register_spi_bitbang_master(&bitbang_spi_master_nicintel))
return 1;
return 0;
}
|
