iCE40/fpga-interchange-schema

	Commit message (Expand)	Author	Age	Files	Lines
*	interchange: Add sub-tiles, needed for Nexus FASM generation	gatecat	2021-05-25	1	-0/+10
*	Merge pull request #42 from gatecat/macro-param-map	gatecat	2021-05-21	1	-1/+49
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\| *	Add parameter mapping rules for macros	gatecat	2021-05-12	1	-1/+41
\| *	Allow macro expansions conditional on parameter match	gatecat	2021-04-22	1	-0/+8
* \|	schema: physical: add site information to physicalPip	Alessandro Comodi	2021-05-20	1	-0/+8
* \|	Merge pull request #43 from gatecat/document-lib-names	gatecat	2021-05-20	1	-1/+4
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\| * \|	Add a documented requirement for primLibs library names	gatecat	2021-04-23	1	-1/+4
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* /	Add wire types and categories	gatecat	2021-04-21	1	-0/+29
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*	Add specification of default cell pin values	gatecat	2021-04-19	1	-0/+30
*	Fix examples for format definitions, and add tombstone.	Keith Rothman	2021-03-29	1	-2/+5
*	Removing tile pattern index for now.	clavin	2021-03-29	1	-1/+0
*	Add DeviceResources to cxx_static Makefile and C++ namespace.	Keith Rothman	2021-03-22	1	-0/+3
*	Add entries for default parameters, and how to present parameters as strings.	Keith Rothman	2021-03-22	2	-3/+76
*	Have at least 2 members in LUT equation union.	Keith Rothman	2021-02-24	1	-0/+1
*	Add INIT parameter field and add comments to LUT section.	Keith Rothman	2021-02-23	1	-2/+30
*	Add missing constant information to device database.	Keith Rothman	2021-02-19	1	-0/+19
*	Add LUT definitions to DeviceResources.	Keith Rothman	2021-02-12	1	-0/+32
*	Add C++ namespace definitions.	Keith Rothman	2021-02-12	2	-2/+8
*	Unify on unix line endings.	Keith Rothman	2021-02-12	2	-293/+293
*	Transfering from Xilinx/RapidWright	Chris Lavin	2021-02-12	4	-0/+834