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author | Tristan Gingold <tgingold@free.fr> | 2017-02-13 21:27:58 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-02-13 21:27:58 +0100 |
commit | 37f32aeba8adf5696f64b4d17298a7e3e5c4a38e (patch) | |
tree | e185c9e6bcbc41f11153e5c4dec717ca28ef2490 | |
parent | d343b8fc2861db2dce9d860d517c6cc83acbdc75 (diff) | |
download | ghdl-yosys-plugin-37f32aeba8adf5696f64b4d17298a7e3e5c4a38e.tar.gz ghdl-yosys-plugin-37f32aeba8adf5696f64b4d17298a7e3e5c4a38e.tar.bz2 ghdl-yosys-plugin-37f32aeba8adf5696f64b4d17298a7e3e5c4a38e.zip |
Add reproducers for #4
-rw-r--r-- | testsuite/issue4/counter8.vhdl | 23 | ||||
-rwxr-xr-x | testsuite/issue4/testsuite.sh | 14 | ||||
-rw-r--r-- | testsuite/issue4/vector.vhdl | 16 | ||||
-rw-r--r-- | testsuite/testenv.sh | 30 |
4 files changed, 83 insertions, 0 deletions
diff --git a/testsuite/issue4/counter8.vhdl b/testsuite/issue4/counter8.vhdl new file mode 100644 index 0000000..2067e23 --- /dev/null +++ b/testsuite/issue4/counter8.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counter8 is + port (clk : in std_logic; + led0 : out std_logic); +end counter8; + +architecture synth of counter8 is + +begin + + process (clk) + variable temp : unsigned (7 downto 0); + begin + if rising_edge(clk) then + temp:= temp + 1; + led0 <= temp(0); + end if; + end process; + +end synth; diff --git a/testsuite/issue4/testsuite.sh b/testsuite/issue4/testsuite.sh new file mode 100755 index 0000000..9eaedbc --- /dev/null +++ b/testsuite/issue4/testsuite.sh @@ -0,0 +1,14 @@ +#!/bin/sh + +. ../testenv.sh + +analyze novector.vhdl +synth no_vector + +analyze counter8.vhdl +synth counter8 + +analyze vector.vhdl +synth vector + +clean diff --git a/testsuite/issue4/vector.vhdl b/testsuite/issue4/vector.vhdl new file mode 100644 index 0000000..de74ea9 --- /dev/null +++ b/testsuite/issue4/vector.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port (led0: out std_logic); +end vector; + +architecture synth of vector is + +signal v : std_logic_vector(7 downto 0); + +begin + v <= std_logic_vector'("10101010"); + led0 <= v(0); +end synth; diff --git a/testsuite/testenv.sh b/testsuite/testenv.sh new file mode 100644 index 0000000..87aca65 --- /dev/null +++ b/testsuite/testenv.sh @@ -0,0 +1,30 @@ +# Testsuite environment + +set -e + +if [ x"$GHDL" = x ]; then + GHDL=ghdl +fi + +if [ x"$YOSYS" = x ]; then + YOSYS="yosys -m ../../ghdl.so" +fi + +analyze () +{ + echo "analyze $@" + "$GHDL" -a $GHDL_STD_FLAGS $GHDL_FLAGS $@ +} + +synth () +{ + echo "synthesize $@" + "$YOSYS" -p "ghdl $@; synth_ice40 -blif out.blif" +} + +clean () +{ + echo "Remove work library" + "$GHDL" --remove $GHDL_STD_FLAGS + rm -f out.blif +} |