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| author | Tristan Gingold <tgingold@free.fr> | 2017-02-26 08:49:50 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-02-26 08:49:50 +0100 |
| commit | 3b0c85f2ffd9471a8abc5eef1b0f15699241d66a (patch) | |
| tree | 75414f50a43e28846c76be6e4f5dbecd7835de6e | |
| parent | 100b4da994c446e4d3d661d643aa0395296f1355 (diff) | |
| download | ghdl-yosys-plugin-3b0c85f2ffd9471a8abc5eef1b0f15699241d66a.tar.gz ghdl-yosys-plugin-3b0c85f2ffd9471a8abc5eef1b0f15699241d66a.tar.bz2 ghdl-yosys-plugin-3b0c85f2ffd9471a8abc5eef1b0f15699241d66a.zip | |
Handle nor, nand, xnor.
| -rw-r--r-- | ghdl/ghdl.cc | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index 9c5dfd4..1a1212c 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -191,6 +191,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_And: case Id_Or: case Id_Xor: + case Id_Nand: + case Id_Nor: + case Id_Xnor: case Id_Add: case Id_Mux2: case Id_Mux4: @@ -246,6 +249,25 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Xor: module->addXor(to_str(iname), IN(0), IN(1), OUT(0)); break; + case Id_Nand: + { + SigSpec r = OUT(0); + RTLIL::Wire *w = module->addWire(NEW_ID, r.size()); + module->addAnd(NEW_ID, IN(0), IN(1), w); + module->addNot(to_str(iname), w, r); + } + break; + case Id_Nor: + { + SigSpec r = OUT(0); + RTLIL::Wire *w = module->addWire(NEW_ID, r.size()); + module->addOr(NEW_ID, IN(0), IN(1), w); + module->addNot(to_str(iname), w, r); + } + break; + case Id_Xnor: + module->addXnor(to_str(iname), IN(0), IN(1), OUT(0)); + break; case Id_Add: module->addAdd(to_str(iname), IN(0), IN(1), OUT(0)); break; |