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| author | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:24:33 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:24:33 +0100 |
| commit | 41222e9d1193dedc407158352f7180dc6d5ee655 (patch) | |
| tree | 9c24526d9d46e2d4a649c84379c66ebfed713818 | |
| parent | b123ccd6296f689d9e9407cb571bc5b496bc9c09 (diff) | |
| download | ghdl-yosys-plugin-41222e9d1193dedc407158352f7180dc6d5ee655.tar.gz ghdl-yosys-plugin-41222e9d1193dedc407158352f7180dc6d5ee655.tar.bz2 ghdl-yosys-plugin-41222e9d1193dedc407158352f7180dc6d5ee655.zip | |
handle mem_rd_sync gates.
| -rw-r--r-- | src/ghdl.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 3683b29..ef3113a 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -278,6 +278,7 @@ static void import_memory(RTLIL::Module *module, std::vector<RTLIL::Wire *> &net Net dat; switch(get_id(port_inst)) { case Id_Mem_Rd: + case Id_Mem_Rd_Sync: dat = get_output(port_inst, 1); addr = get_input_net(port_inst, 1); nbr_rd++; @@ -352,6 +353,13 @@ static void import_memory(RTLIL::Module *module, std::vector<RTLIL::Wire *> &net rd_data.append(OUT(1)); rd_en.append(Const(1, 1)); break; + case Id_Mem_Rd_Sync: + rd_clk_en.push_back(RTLIL::State::S1); + rd_clk.append(IN(2)); + rd_addr.append(IN(1)); + rd_data.append(OUT(1)); + rd_en.append(IN(3)); + break; case Id_Mem_Wr_Sync: wr_clk.append(IN(2)); wr_addr.append(IN(1)); @@ -497,6 +505,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Anyconst: case Id_Anyseq: case Id_Mem_Rd: + case Id_Mem_Rd_Sync: case Id_User_None: for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) { Net o = get_output(inst, idx); @@ -748,6 +757,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) memories.push_back(inst); break; case Id_Mem_Rd: + case Id_Mem_Rd_Sync: case Id_Mem_Wr_Sync: break; case Id_Const_UB32: |