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authorJulianKemmerer <julian.v.kemmerer@gmail.com>2020-12-19 00:12:04 -0500
committertgingold <tgingold@users.noreply.github.com>2020-12-19 07:47:46 +0100
commit6671d0475fb32d549307d3a864455e6915c39aa3 (patch)
treedcb6a7efcc037d3b08ec4d9b2144d741c4b9dd3d
parent0afee7f15b57197d0ae0bcb3b6ff74d16bbc1696 (diff)
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Fix mult18x18d component to match yosys verilog
-rw-r--r--library/ecp5u/components.vhdl520
1 files changed, 260 insertions, 260 deletions
diff --git a/library/ecp5u/components.vhdl b/library/ecp5u/components.vhdl
index e4a40b2..3f1f428 100644
--- a/library/ecp5u/components.vhdl
+++ b/library/ecp5u/components.vhdl
@@ -1486,267 +1486,267 @@ component mult18x18c is
signedp : out std_logic );
end component;
-component mult18x18d is
+component MULT18X18D is
generic (
- reg_inputa_clk : string := "NONE";
- reg_inputa_ce : string := "CE0";
- reg_inputa_rst : string := "RST0";
- reg_inputb_clk : string := "NONE";
- reg_inputb_ce : string := "CE0";
- reg_inputb_rst : string := "RST0";
- reg_inputc_clk : string := "NONE";
- reg_inputc_ce : string := "CE0";
- reg_inputc_rst : string := "RST0";
- reg_pipeline_clk : string := "NONE";
- reg_pipeline_ce : string := "CE0";
- reg_pipeline_rst : string := "RST0";
- reg_output_clk : string := "NONE";
- reg_output_ce : string := "CE0";
- reg_output_rst : string := "RST0";
- clk0_div : string := "ENABLED";
- clk1_div : string := "ENABLED";
- clk2_div : string := "ENABLED";
- clk3_div : string := "ENABLED";
- highspeed_clk : string := "NONE";
- gsr : string := "ENABLED";
- cas_match_reg : string := "FALSE";
- sourceb_mode : string := "B_SHIFT";
- mult_bypass : string := "DISABLED";
- resetmode : string := "SYNC" );
- port (
- a17 : in std_logic;
- a16 : in std_logic;
- a15 : in std_logic;
- a14 : in std_logic;
- a13 : in std_logic;
- a12 : in std_logic;
- a11 : in std_logic;
- a10 : in std_logic;
- a9 : in std_logic;
- a8 : in std_logic;
- a7 : in std_logic;
- a6 : in std_logic;
- a5 : in std_logic;
- a4 : in std_logic;
- a3 : in std_logic;
- a2 : in std_logic;
- a1 : in std_logic;
- a0 : in std_logic;
- b17 : in std_logic;
- b16 : in std_logic;
- b15 : in std_logic;
- b14 : in std_logic;
- b13 : in std_logic;
- b12 : in std_logic;
- b11 : in std_logic;
- b10 : in std_logic;
- b9 : in std_logic;
- b8 : in std_logic;
- b7 : in std_logic;
- b6 : in std_logic;
- b5 : in std_logic;
- b4 : in std_logic;
- b3 : in std_logic;
- b2 : in std_logic;
- b1 : in std_logic;
- b0 : in std_logic;
- c17 : in std_logic;
- c16 : in std_logic;
- c15 : in std_logic;
- c14 : in std_logic;
- c13 : in std_logic;
- c12 : in std_logic;
- c11 : in std_logic;
- c10 : in std_logic;
- c9 : in std_logic;
- c8 : in std_logic;
- c7 : in std_logic;
- c6 : in std_logic;
- c5 : in std_logic;
- c4 : in std_logic;
- c3 : in std_logic;
- c2 : in std_logic;
- c1 : in std_logic;
- c0 : in std_logic;
- signeda : in std_logic;
- signedb : in std_logic;
- sourcea : in std_logic;
- sourceb : in std_logic;
- clk3 : in std_logic;
- clk2 : in std_logic;
- clk1 : in std_logic;
- clk0 : in std_logic;
- ce3 : in std_logic;
- ce2 : in std_logic;
- ce1 : in std_logic;
- ce0 : in std_logic;
- rst3 : in std_logic;
- rst2 : in std_logic;
- rst1 : in std_logic;
- rst0 : in std_logic;
- sria17 : in std_logic;
- sria16 : in std_logic;
- sria15 : in std_logic;
- sria14 : in std_logic;
- sria13 : in std_logic;
- sria12 : in std_logic;
- sria11 : in std_logic;
- sria10 : in std_logic;
- sria9 : in std_logic;
- sria8 : in std_logic;
- sria7 : in std_logic;
- sria6 : in std_logic;
- sria5 : in std_logic;
- sria4 : in std_logic;
- sria3 : in std_logic;
- sria2 : in std_logic;
- sria1 : in std_logic;
- sria0 : in std_logic;
- srib17 : in std_logic;
- srib16 : in std_logic;
- srib15 : in std_logic;
- srib14 : in std_logic;
- srib13 : in std_logic;
- srib12 : in std_logic;
- srib11 : in std_logic;
- srib10 : in std_logic;
- srib9 : in std_logic;
- srib8 : in std_logic;
- srib7 : in std_logic;
- srib6 : in std_logic;
- srib5 : in std_logic;
- srib4 : in std_logic;
- srib3 : in std_logic;
- srib2 : in std_logic;
- srib1 : in std_logic;
- srib0 : in std_logic;
- sroa17 : out std_logic;
- sroa16 : out std_logic;
- sroa15 : out std_logic;
- sroa14 : out std_logic;
- sroa13 : out std_logic;
- sroa12 : out std_logic;
- sroa11 : out std_logic;
- sroa10 : out std_logic;
- sroa9 : out std_logic;
- sroa8 : out std_logic;
- sroa7 : out std_logic;
- sroa6 : out std_logic;
- sroa5 : out std_logic;
- sroa4 : out std_logic;
- sroa3 : out std_logic;
- sroa2 : out std_logic;
- sroa1 : out std_logic;
- sroa0 : out std_logic;
- srob17 : out std_logic;
- srob16 : out std_logic;
- srob15 : out std_logic;
- srob14 : out std_logic;
- srob13 : out std_logic;
- srob12 : out std_logic;
- srob11 : out std_logic;
- srob10 : out std_logic;
- srob9 : out std_logic;
- srob8 : out std_logic;
- srob7 : out std_logic;
- srob6 : out std_logic;
- srob5 : out std_logic;
- srob4 : out std_logic;
- srob3 : out std_logic;
- srob2 : out std_logic;
- srob1 : out std_logic;
- srob0 : out std_logic;
- roa17 : out std_logic;
- roa16 : out std_logic;
- roa15 : out std_logic;
- roa14 : out std_logic;
- roa13 : out std_logic;
- roa12 : out std_logic;
- roa11 : out std_logic;
- roa10 : out std_logic;
- roa9 : out std_logic;
- roa8 : out std_logic;
- roa7 : out std_logic;
- roa6 : out std_logic;
- roa5 : out std_logic;
- roa4 : out std_logic;
- roa3 : out std_logic;
- roa2 : out std_logic;
- roa1 : out std_logic;
- roa0 : out std_logic;
- rob17 : out std_logic;
- rob16 : out std_logic;
- rob15 : out std_logic;
- rob14 : out std_logic;
- rob13 : out std_logic;
- rob12 : out std_logic;
- rob11 : out std_logic;
- rob10 : out std_logic;
- rob9 : out std_logic;
- rob8 : out std_logic;
- rob7 : out std_logic;
- rob6 : out std_logic;
- rob5 : out std_logic;
- rob4 : out std_logic;
- rob3 : out std_logic;
- rob2 : out std_logic;
- rob1 : out std_logic;
- rob0 : out std_logic;
- roc17 : out std_logic;
- roc16 : out std_logic;
- roc15 : out std_logic;
- roc14 : out std_logic;
- roc13 : out std_logic;
- roc12 : out std_logic;
- roc11 : out std_logic;
- roc10 : out std_logic;
- roc9 : out std_logic;
- roc8 : out std_logic;
- roc7 : out std_logic;
- roc6 : out std_logic;
- roc5 : out std_logic;
- roc4 : out std_logic;
- roc3 : out std_logic;
- roc2 : out std_logic;
- roc1 : out std_logic;
- roc0 : out std_logic;
- p35 : out std_logic;
- p34 : out std_logic;
- p33 : out std_logic;
- p32 : out std_logic;
- p31 : out std_logic;
- p30 : out std_logic;
- p29 : out std_logic;
- p28 : out std_logic;
- p27 : out std_logic;
- p26 : out std_logic;
- p25 : out std_logic;
- p24 : out std_logic;
- p23 : out std_logic;
- p22 : out std_logic;
- p21 : out std_logic;
- p20 : out std_logic;
- p19 : out std_logic;
- p18 : out std_logic;
- p17 : out std_logic;
- p16 : out std_logic;
- p15 : out std_logic;
- p14 : out std_logic;
- p13 : out std_logic;
- p12 : out std_logic;
- p11 : out std_logic;
- p10 : out std_logic;
- p9 : out std_logic;
- p8 : out std_logic;
- p7 : out std_logic;
- p6 : out std_logic;
- p5 : out std_logic;
- p4 : out std_logic;
- p3 : out std_logic;
- p2 : out std_logic;
- p1 : out std_logic;
- p0 : out std_logic;
- signedp : out std_logic );
+ REG_INPUTA_CLK : string := "NONE";
+ REG_INPUTA_CE : string := "CE0";
+ REG_INPUTA_RST : string := "RST0";
+ REG_INPUTB_CLK : string := "NONE";
+ REG_INPUTB_CE : string := "CE0";
+ REG_INPUTB_RST : string := "RST0";
+ REG_INPUTC_CLK : string := "NONE";
+ --reg_inputc_ce : string := "CE0";
+ --reg_inputc_rst : string := "RST0";
+ REG_PIPELINE_CLK : string := "NONE";
+ REG_PIPELINE_CE : string := "CE0";
+ REG_PIPELINE_RST : string := "RST0";
+ REG_OUTPUT_CLK : string := "NONE";
+ --reg_output_ce : string := "CE0";
+ --reg_output_rst : string := "RST0";
+ CLK0_DIV : string := "ENABLED";
+ CLK1_DIV : string := "ENABLED";
+ CLK2_DIV : string := "ENABLED";
+ CLK3_DIV : string := "ENABLED";
+ --highspeed_clk : string := "NONE";
+ GSR : string := "ENABLED";
+ --Cas_match_reg : string := "FALSE";
+ SOURCEB_MODE : string := "B_SHIFT";
+ --mult_bypass : string := "DISABLED";
+ RESETMODE : string := "SYNC" );
+ port (
+ A17 : in std_logic;
+ A16 : in std_logic;
+ A15 : in std_logic;
+ A14 : in std_logic;
+ A13 : in std_logic;
+ A12 : in std_logic;
+ A11 : in std_logic;
+ A10 : in std_logic;
+ A9 : in std_logic;
+ A8 : in std_logic;
+ A7 : in std_logic;
+ A6 : in std_logic;
+ A5 : in std_logic;
+ A4 : in std_logic;
+ A3 : in std_logic;
+ A2 : in std_logic;
+ A1 : in std_logic;
+ A0 : in std_logic;
+ B17 : in std_logic;
+ B16 : in std_logic;
+ B15 : in std_logic;
+ B14 : in std_logic;
+ B13 : in std_logic;
+ B12 : in std_logic;
+ B11 : in std_logic;
+ B10 : in std_logic;
+ B9 : in std_logic;
+ B8 : in std_logic;
+ B7 : in std_logic;
+ B6 : in std_logic;
+ B5 : in std_logic;
+ B4 : in std_logic;
+ B3 : in std_logic;
+ B2 : in std_logic;
+ B1 : in std_logic;
+ B0 : in std_logic;
+ C17 : in std_logic;
+ C16 : in std_logic;
+ C15 : in std_logic;
+ C14 : in std_logic;
+ C13 : in std_logic;
+ C12 : in std_logic;
+ C11 : in std_logic;
+ C10 : in std_logic;
+ C9 : in std_logic;
+ C8 : in std_logic;
+ C7 : in std_logic;
+ C6 : in std_logic;
+ C5 : in std_logic;
+ C4 : in std_logic;
+ C3 : in std_logic;
+ C2 : in std_logic;
+ C1 : in std_logic;
+ C0 : in std_logic;
+ SIGNEDA : in std_logic;
+ SIGNEDB : in std_logic;
+ SOURCEA : in std_logic;
+ SOURCEB : in std_logic;
+ CLK3 : in std_logic;
+ CLK2 : in std_logic;
+ CLK1 : in std_logic;
+ CLK0 : in std_logic;
+ CE3 : in std_logic;
+ CE2 : in std_logic;
+ CE1 : in std_logic;
+ CE0 : in std_logic;
+ RST3 : in std_logic;
+ RST2 : in std_logic;
+ RST1 : in std_logic;
+ RST0 : in std_logic;
+ -- SRIA17 : in std_logic;
+ -- SRIA16 : in std_logic;
+ -- SRIA15 : in std_logic;
+ -- SRIA14 : in std_logic;
+ -- SRIA13 : in std_logic;
+ -- SRIA12 : in std_logic;
+ -- SRIA11 : in std_logic;
+ -- SRIA10 : in std_logic;
+ -- SRIA9 : in std_logic;
+ -- SRIA8 : in std_logic;
+ -- SRIA7 : in std_logic;
+ -- SRIA6 : in std_logic;
+ -- SRIA5 : in std_logic;
+ -- SRIA4 : in std_logic;
+ -- SRIA3 : in std_logic;
+ -- SRIA2 : in std_logic;
+ -- SRIA1 : in std_logic;
+ -- SRIA0 : in std_logic;
+ -- SRIB17 : in std_logic;
+ -- SRIB16 : in std_logic;
+ -- SRIB15 : in std_logic;
+ -- SRIB14 : in std_logic;
+ -- SRIB13 : in std_logic;
+ -- SRIB12 : in std_logic;
+ -- SRIB11 : in std_logic;
+ -- SRIB10 : in std_logic;
+ -- SRIB9 : in std_logic;
+ -- SRIB8 : in std_logic;
+ -- SRIB7 : in std_logic;
+ -- SRIB6 : in std_logic;
+ -- SRIB5 : in std_logic;
+ -- SRIB4 : in std_logic;
+ -- SRIB3 : in std_logic;
+ -- SRIB2 : in std_logic;
+ -- SRIB1 : in std_logic;
+ -- SRIB0 : in std_logic;
+ SROA17 : out std_logic;
+ SROA16 : out std_logic;
+ SROA15 : out std_logic;
+ SROA14 : out std_logic;
+ SROA13 : out std_logic;
+ SROA12 : out std_logic;
+ SROA11 : out std_logic;
+ SROA10 : out std_logic;
+ SROA9 : out std_logic;
+ SROA8 : out std_logic;
+ SROA7 : out std_logic;
+ SROA6 : out std_logic;
+ SROA5 : out std_logic;
+ SROA4 : out std_logic;
+ SROA3 : out std_logic;
+ SROA2 : out std_logic;
+ SROA1 : out std_logic;
+ SROA0 : out std_logic;
+ SROB17 : out std_logic;
+ SROB16 : out std_logic;
+ SROB15 : out std_logic;
+ SROB14 : out std_logic;
+ SROB13 : out std_logic;
+ SROB12 : out std_logic;
+ SROB11 : out std_logic;
+ SROB10 : out std_logic;
+ SROB9 : out std_logic;
+ SROB8 : out std_logic;
+ SROB7 : out std_logic;
+ SROB6 : out std_logic;
+ SROB5 : out std_logic;
+ SROB4 : out std_logic;
+ SROB3 : out std_logic;
+ SROB2 : out std_logic;
+ SROB1 : out std_logic;
+ SROB0 : out std_logic;
+ ROA17 : out std_logic;
+ ROA16 : out std_logic;
+ ROA15 : out std_logic;
+ ROA14 : out std_logic;
+ ROA13 : out std_logic;
+ ROA12 : out std_logic;
+ ROA11 : out std_logic;
+ ROA10 : out std_logic;
+ ROA9 : out std_logic;
+ ROA8 : out std_logic;
+ ROA7 : out std_logic;
+ ROA6 : out std_logic;
+ ROA5 : out std_logic;
+ ROA4 : out std_logic;
+ ROA3 : out std_logic;
+ ROA2 : out std_logic;
+ ROA1 : out std_logic;
+ ROA0 : out std_logic;
+ ROB17 : out std_logic;
+ ROB16 : out std_logic;
+ ROB15 : out std_logic;
+ ROB14 : out std_logic;
+ ROB13 : out std_logic;
+ ROB12 : out std_logic;
+ ROB11 : out std_logic;
+ ROB10 : out std_logic;
+ ROB9 : out std_logic;
+ ROB8 : out std_logic;
+ ROB7 : out std_logic;
+ ROB6 : out std_logic;
+ ROB5 : out std_logic;
+ ROB4 : out std_logic;
+ ROB3 : out std_logic;
+ ROB2 : out std_logic;
+ ROB1 : out std_logic;
+ ROB0 : out std_logic;
+ ROC17 : out std_logic;
+ ROC16 : out std_logic;
+ ROC15 : out std_logic;
+ ROC14 : out std_logic;
+ ROC13 : out std_logic;
+ ROC12 : out std_logic;
+ ROC11 : out std_logic;
+ ROC10 : out std_logic;
+ ROC9 : out std_logic;
+ ROC8 : out std_logic;
+ ROC7 : out std_logic;
+ ROC6 : out std_logic;
+ ROC5 : out std_logic;
+ ROC4 : out std_logic;
+ ROC3 : out std_logic;
+ ROC2 : out std_logic;
+ ROC1 : out std_logic;
+ ROC0 : out std_logic;
+ P35 : out std_logic;
+ P34 : out std_logic;
+ P33 : out std_logic;
+ P32 : out std_logic;
+ P31 : out std_logic;
+ P30 : out std_logic;
+ P29 : out std_logic;
+ P28 : out std_logic;
+ P27 : out std_logic;
+ P26 : out std_logic;
+ P25 : out std_logic;
+ P24 : out std_logic;
+ P23 : out std_logic;
+ P22 : out std_logic;
+ P21 : out std_logic;
+ P20 : out std_logic;
+ P19 : out std_logic;
+ P18 : out std_logic;
+ P17 : out std_logic;
+ P16 : out std_logic;
+ P15 : out std_logic;
+ P14 : out std_logic;
+ P13 : out std_logic;
+ P12 : out std_logic;
+ P11 : out std_logic;
+ P10 : out std_logic;
+ P9 : out std_logic;
+ P8 : out std_logic;
+ P7 : out std_logic;
+ P6 : out std_logic;
+ P5 : out std_logic;
+ P4 : out std_logic;
+ P3 : out std_logic;
+ P2 : out std_logic;
+ P1 : out std_logic;
+ P0 : out std_logic;
+ SIGNEDP : out std_logic );
end component;
component alu24a is