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| author | T. Meissner <programming@goodcleanfun.de> | 2019-10-05 07:35:01 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-05 07:35:01 +0200 |
| commit | 667e33c2029070b24681b4483c5384eab47cb3a8 (patch) | |
| tree | a6e986d31875d907df181b62cac3f1f7a01fa758 | |
| parent | 366d22bac43caec422b0628c08b5986b0199e4bf (diff) | |
| download | ghdl-yosys-plugin-667e33c2029070b24681b4483c5384eab47cb3a8.tar.gz ghdl-yosys-plugin-667e33c2029070b24681b4483c5384eab47cb3a8.tar.bz2 ghdl-yosys-plugin-667e33c2029070b24681b4483c5384eab47cb3a8.zip | |
Handle Const_X & Const_Z (#49)
| -rw-r--r-- | src/ghdl.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index ed19b1a..b027204 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -94,6 +94,14 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) } return RTLIL::SigSpec(RTLIL::Const(bits)); } + case Id_Const_Z: + { + return SigSpec(RTLIL::State::Sz, get_width(n)); + } + case Id_Const_X: + { + return SigSpec(RTLIL::State::Sx, get_width(n)); + } case Id_Const_Log: case Id_Const_UL32: { @@ -311,6 +319,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_UL32: case Id_Const_Bit: case Id_Const_Log: + case Id_Const_Z: + case Id_Const_X: case Id_Uextend: case Id_Utrunc: case Id_Strunc: @@ -485,6 +495,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_UL32: case Id_Const_Bit: case Id_Const_Log: + case Id_Const_Z: + case Id_Const_X: case Id_Uextend: case Id_Utrunc: case Id_Strunc: |