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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-16 10:22:51 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-16 10:22:51 +0100 |
| commit | 83e16d4bdde512fb25a507a2550677a428881556 (patch) | |
| tree | 00b2a533719904288460aeac25e35b0671072982 | |
| parent | e27db89e7e9f80e0c739e8fdb043a7dff72b0a0a (diff) | |
| download | ghdl-yosys-plugin-83e16d4bdde512fb25a507a2550677a428881556.tar.gz ghdl-yosys-plugin-83e16d4bdde512fb25a507a2550677a428881556.tar.bz2 ghdl-yosys-plugin-83e16d4bdde512fb25a507a2550677a428881556.zip | |
Adjust pr61 testcase to avoid constant propagation.
| -rw-r--r-- | testsuite/issues/pr61/vector.vhdl | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl index 61a0d67..ea83bc2 100644 --- a/testsuite/issues/pr61/vector.vhdl +++ b/testsuite/issues/pr61/vector.vhdl @@ -8,8 +8,12 @@ entity vector is end vector; architecture synth of vector is + signal v1 : signed (63 downto 0); + signal u1 : unsigned (63 downto 0); begin - v <= signed'(x"0ffffffffffffff0")+(-1); - u <= unsigned'(x"00ffffffffffff00")+4294967290; + v1 <= x"0ffffffffffffff0"; + v <= v1+(-1); + u1 <= x"00ffffffffffff00"; + u <= u1 +4294967290; end synth; |