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| author | rlee287 <rlee287@yahoo.com> | 2020-05-27 12:49:42 -0700 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2020-05-28 07:27:13 +0200 |
| commit | 8e1a7aac07bdddeec71614574e886c9438848bb2 (patch) | |
| tree | 60c1bd445effd6be99a391695e3e895d0f916fe1 | |
| parent | 49725db159c752ef616715210c2ee7bf37187d33 (diff) | |
| download | ghdl-yosys-plugin-8e1a7aac07bdddeec71614574e886c9438848bb2.tar.gz ghdl-yosys-plugin-8e1a7aac07bdddeec71614574e886c9438848bb2.tar.bz2 ghdl-yosys-plugin-8e1a7aac07bdddeec71614574e886c9438848bb2.zip | |
Add reduce_xor support to the Yosys plugin
This is a followup for ghdl/ghdl issue 1342
| -rw-r--r-- | src/ghdl.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 0d91bb4..d1e5cd8 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -663,6 +663,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Abs: case Id_Red_Or: case Id_Red_And: + case Id_Red_Xor: case Id_Lsr: case Id_Lsl: case Id_Asr: @@ -840,6 +841,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Red_And: module->addReduceAnd(to_str(iname), IN(0), OUT(0)); break; + case Id_Red_Xor: + module->addReduceXor(to_str(iname), IN(0), OUT(0)); + break; case Id_Lsl: module->addShl(to_str(iname), IN(0), IN(1), OUT(0)); break; |