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| author | Tristan Gingold <tgingold@free.fr> | 2021-10-02 19:20:25 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-10-02 19:21:21 +0200 |
| commit | a0b84cc52e26bfaf35a947a8e7e76b576b4d92c0 (patch) | |
| tree | 886736447cfcbfaf00eb1a2e359801321ce2e0b6 | |
| parent | d7536e61da6f8b88b5f784b1f60161805b2c4009 (diff) | |
| download | ghdl-yosys-plugin-a0b84cc52e26bfaf35a947a8e7e76b576b4d92c0.tar.gz ghdl-yosys-plugin-a0b84cc52e26bfaf35a947a8e7e76b576b4d92c0.tar.bz2 ghdl-yosys-plugin-a0b84cc52e26bfaf35a947a8e7e76b576b4d92c0.zip | |
ghdl.cc: always create a wire for signal/isignal. Fix #158
| -rw-r--r-- | src/ghdl.cc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index c107d78..7b36042 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -179,8 +179,6 @@ static RTLIL::SigSpec get_src_extract(std::vector<RTLIL::Wire *> &net_map, Net n { Instance inst = get_net_parent(n); switch(get_id(inst)) { - case Id_Signal: - case Id_Isignal: case Id_Port: case Id_Output: return get_src_extract(net_map, get_input_net(inst, 0), off, wd); @@ -213,8 +211,6 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) Instance inst = get_net_parent(n); switch(get_id(inst)) { #define IN(N) get_src(net_map, get_input_net(inst, (N))) - case Id_Signal: - case Id_Isignal: case Id_Port: case Id_Output: return IN(0); @@ -751,6 +747,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Mem_Rd: case Id_Mem_Rd_Sync: case Id_Tri: + case Id_Signal: + case Id_Isignal: case Id_Resolver: case Id_User_None: case Id_User_Parameters: @@ -780,9 +778,6 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Mem_Wr_Sync: // Handled by import_memory. break; - case Id_Signal: - case Id_Isignal: - break; case Id_Port: case Id_Const_UB32: case Id_Const_SB32: @@ -1094,6 +1089,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) break; case Id_Signal: case Id_Isignal: + module->connect(OUT (0), IN (0)); break; case Id_Output: case Id_Port: |