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| author | T. Meissner <programming@goodcleanfun.de> | 2019-09-20 03:48:49 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-09-20 03:48:49 +0200 |
| commit | ba8da81f036d761adbb69331d666bc90b3b3bf11 (patch) | |
| tree | c1cfec811b9d086528e654b9bc57f4182b4bb91b | |
| parent | e3036dcd6b0cdc8bf885d943a891d9c68c565934 (diff) | |
| download | ghdl-yosys-plugin-ba8da81f036d761adbb69331d666bc90b3b3bf11.tar.gz ghdl-yosys-plugin-ba8da81f036d761adbb69331d666bc90b3b3bf11.tar.bz2 ghdl-yosys-plugin-ba8da81f036d761adbb69331d666bc90b3b3bf11.zip | |
Handle covers (#43)
| -rw-r--r-- | src/ghdl.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 421f1b4..a758928 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -272,6 +272,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Red_And: case Id_Assert: // No output case Id_Assume: // No output + case Id_Cover: // No output case Id_User_None: for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) { Net o = get_output(inst, idx); @@ -456,6 +457,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Assume: module->addAssume(to_str(iname), IN(0), State::S1); break; + case Id_Cover: + module->addCover(to_str(iname), IN(0), State::S1); + break; case Id_Const_UB32: case Id_Const_UL32: case Id_Uextend: |