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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-03 18:44:15 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-03 18:44:15 +0200 |
| commit | c5a6898fa02bec18227c121a8c8ebf30fc312c89 (patch) | |
| tree | 56d59420360c39fdf0c2cf96b1e97dcfbe6f24cb | |
| parent | ea1f7258eae67563597934d98381b610429d73cd (diff) | |
| download | ghdl-yosys-plugin-c5a6898fa02bec18227c121a8c8ebf30fc312c89.tar.gz ghdl-yosys-plugin-c5a6898fa02bec18227c121a8c8ebf30fc312c89.tar.bz2 ghdl-yosys-plugin-c5a6898fa02bec18227c121a8c8ebf30fc312c89.zip | |
Handle assertions.
| -rw-r--r-- | ghdl/ghdl.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index df40695..05ba354 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -216,6 +216,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Eq: case Id_Ne: case Id_Not: + case Id_Assert: // No output for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) { Net o = get_output(inst, idx); // The wire may have been created for an output @@ -235,9 +236,11 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Concat2: case Id_Concat3: case Id_Concat4: - case Id_Edge: // Ignored. // Skip: these won't create cells. break; + case Id_Edge: + // The cell is ignored. + break; default: log_cmd_error("Unsupported(1): instance %s of %s.\n", to_str(get_instance_name(inst)).c_str(), @@ -332,6 +335,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Output: module->connect(OUT (0), IN (0)); break; + case Id_Assert: + module->addAssert(to_str(iname), IN(0), State::S1); + break; case Id_Const_UB32: case Id_Uextend: case Id_Extract: |