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| author | Tristan Gingold <tgingold@free.fr> | 2017-02-26 07:49:30 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-02-26 07:50:30 +0100 |
| commit | d85deb6af3832b680065e5a906b11867533b9bbd (patch) | |
| tree | 68bbe5a119d85e0441d11d66dbb1697c37a7c836 | |
| parent | d230a4374a09ac6dc4ecdaf3371a23ac494e68ba (diff) | |
| download | ghdl-yosys-plugin-d85deb6af3832b680065e5a906b11867533b9bbd.tar.gz ghdl-yosys-plugin-d85deb6af3832b680065e5a906b11867533b9bbd.tar.bz2 ghdl-yosys-plugin-d85deb6af3832b680065e5a906b11867533b9bbd.zip | |
Support or and xor gates
Fix #11
| -rw-r--r-- | ghdl/ghdl.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index 78d1571..9c5dfd4 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -189,6 +189,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) Module_Id id = get_id(im); switch (id) { case Id_And: + case Id_Or: + case Id_Xor: case Id_Add: case Id_Mux2: case Id_Mux4: @@ -238,6 +240,12 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_And: module->addAnd(to_str(iname), IN(0), IN(1), OUT(0)); break; + case Id_Or: + module->addOr(to_str(iname), IN(0), IN(1), OUT(0)); + break; + case Id_Xor: + module->addXor(to_str(iname), IN(0), IN(1), OUT(0)); + break; case Id_Add: module->addAdd(to_str(iname), IN(0), IN(1), OUT(0)); break; |