Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore.

5 files changed, 73 insertions, 78 deletions

diff --git a/examples/ecp5_versa/Makefile b/examples/ecp5_versa/Makefile
index 6031055..2b54e17 100644
--- a/examples/ecp5_versa/Makefile
+++ b/examples/ecp5_versa/Makefile
@@ -21,10 +21,9 @@ VHDL_SYN_FILES += soc_iomap_pkg.vhdl
 VHDL_SYN_FILES += uart.vhdl uart_tx.vhdl uart_rx.vhdl fifobuf.vhdl
 
 TOPLEVEL = versa_ecp5_top
-TOPLEVEL_PARAMETER = _$(CLK_FREQ)
+TOPLEVEL_PARAMETER =
 
 VERILOG_FILES = $(LIB)/wrapper/primitives.v
-VERILOG_FILES += $(LIB)/wrapper/wrapper.v
 VERILOG_FILES += $(LIB)/wrapper/bram.v
 
 SVFFILE = versa_ecp5_top.svf
@@ -39,10 +38,9 @@ lib:
 	mkdir $@
 
 lib/ecp5um-std93.cf: $(LIB)/ecp5u/components.vhdl | lib
-	$(GHDL) -i --workdir=$(dir $@) --work=ecp5um \
-		$< 
+	$(GHDL) -i --workdir=$(dir $@) --work=ecp5um $<
 
-pll_mac.vhd: $(DEPENDENCIES) 
+pll_mac.vhd: $(DEPENDENCIES)
 
 prog: $(SVFFILE)
 	$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) \
diff --git a/examples/ecp5_versa/fifobuf.vhdl b/examples/ecp5_versa/fifobuf.vhdl
index 4981c1d..8122839 100644
--- a/examples/ecp5_versa/fifobuf.vhdl
+++ b/examples/ecp5_versa/fifobuf.vhdl
@@ -62,21 +62,20 @@ architecture behaviour of FifoBuffer is
 
 	component bram_2psync is
 		generic (
-			ADDR_W      : natural := 6;
-			DATA_W      : natural := 16;
-			SYN_RAMTYPE : string := "block_ram"
+			ADDR      : natural := 6;
+			DATA      : natural := 16
 		);
 		port (
 			-- Port A
 			a_we    : in  std_logic;
-			a_addr  : in  unsigned(ADDR_W-1 downto 0);
-			a_write : in  unsigned(DATA_W-1 downto 0);
-			a_read  : out unsigned(DATA_W-1 downto 0);
+			a_addr  : in  unsigned(ADDR-1 downto 0);
+			a_write : in  unsigned(DATA-1 downto 0);
+			a_read  : out unsigned(DATA-1 downto 0);
 			-- Port B
 			b_we    : in  std_logic;
-			b_addr  : in  unsigned(ADDR_W-1 downto 0);
-			b_write : in  unsigned(DATA_W-1 downto 0);
-			b_read  : out unsigned(DATA_W-1 downto 0);
+			b_addr  : in  unsigned(ADDR-1 downto 0);
+			b_write : in  unsigned(DATA-1 downto 0);
+			b_read  : out unsigned(DATA-1 downto 0);
 			clk     : in  std_logic
 		);
 	end component bram_2psync;
@@ -160,8 +159,7 @@ fsm:
 
 ram:
 	bram_2psync
-	generic map ( ADDR_W => ADDR_W, DATA_W => DATA_W,
-		SYN_RAMTYPE => SYN_RAMTYPE)
+	generic map ( ADDR => ADDR_W, DATA => DATA_W)
 	port map (
 		a_we    => '0',
 		a_addr  => optr,
diff --git a/library/ecp5u/components.vhdl b/library/ecp5u/components.vhdl
index d60dbba..e4a40b2 100644
--- a/library/ecp5u/components.vhdl
+++ b/library/ecp5u/components.vhdl
@@ -3733,67 +3733,67 @@ component oscg is
     osc :   out  std_logic  );
 end component;
 
-component ehxplll is
+component EHXPLLL is
   generic (
-    clki_div : integer := 1;
-    clkfb_div : integer := 1;
-    clkop_div : integer := 8;
-    clkos_div : integer := 8;
-    clkos2_div : integer := 8;
-    clkos3_div : integer := 8;
-    clkop_enable : string := "ENABLED";
-    clkos_enable : string := "DISABLED";
-    clkos2_enable : string := "DISABLED";
-    clkos3_enable : string := "DISABLED";
-    clkop_cphase : integer := 0;
-    clkos_cphase : integer := 0;
-    clkos2_cphase : integer := 0;
-    clkos3_cphase : integer := 0;
-    clkop_fphase : integer := 0;
-    clkos_fphase : integer := 0;
-    clkos2_fphase : integer := 0;
-    clkos3_fphase : integer := 0;
-    feedbk_path : string := "CLKOP";
-    clkop_trim_pol : string := "RISING";
-    clkop_trim_delay : integer := 0;
-    clkos_trim_pol : string := "RISING";
-    clkos_trim_delay : integer := 0;
-    outdivider_muxa : string := "DIVA";
-    outdivider_muxb : string := "DIVB";
-    outdivider_muxc : string := "DIVC";
-    outdivider_muxd : string := "DIVD";
-    pll_lock_mode : integer := 0;
-    pll_lock_delay : integer := 200;
-    stdby_enable : string := "DISABLED";
-    refin_reset : string := "DISABLED";
-    sync_enable : string := "DISABLED";
-    int_lock_sticky : string := "ENABLED";
-    dphase_source : string := "DISABLED";
-    pllrst_ena : string := "DISABLED";
-    intfb_wake : string := "DISABLED"  );
-  port (
-    clki :   in  std_logic;
-    clkfb :   in  std_logic;
-    phasesel1 :   in  std_logic;
-    phasesel0 :   in  std_logic;
-    phasedir :   in  std_logic;
-    phasestep :   in  std_logic;
-    phaseloadreg :   in  std_logic;
-    stdby :   in  std_logic;
-    pllwakesync :   in  std_logic;
-    rst :   in  std_logic;
-    enclkop :   in  std_logic;
-    enclkos :   in  std_logic;
-    enclkos2 :   in  std_logic;
-    enclkos3 :   in  std_logic;
-    clkop :   out  std_logic;
-    clkos :   out  std_logic;
-    clkos2 :   out  std_logic;
-    clkos3 :   out  std_logic;
-    lock :   out  std_logic;
-    intlock :   out  std_logic;
-    refclk :   out  std_logic;
-    clkintfb :   out  std_logic  );
+    CLKI_DIV : integer := 1;
+    CLKFB_DIV : integer := 1;
+    CLKOP_DIV : integer := 8;
+    CLKOS_DIV : integer := 8;
+    CLKOS2_DIV : integer := 8;
+    CLKOS3_DIV : integer := 8;
+    CLKOP_ENABLE : string := "ENABLED";
+    CLKOS_ENABLE : string := "DISABLED";
+    CLKOS2_ENABLE : string := "DISABLED";
+    CLKOS3_ENABLE : string := "DISABLED";
+    CLKOP_CPHASE : integer := 0;
+    CLKOS_CPHASE : integer := 0;
+    CLKOS2_CPHASE : integer := 0;
+    CLKOS3_CPHASE : integer := 0;
+    CLKOP_FPHASE : integer := 0;
+    CLKOS_FPHASE : integer := 0;
+    CLKOS2_FPHASE : integer := 0;
+    CLKOS3_FPHASE : integer := 0;
+    FEEDBK_PATH : string := "CLKOP";
+    CLKOP_TRIM_POL : string := "RISING";
+    CLKOP_TRIM_DELAY : integer := 0;
+    CLKOS_TRIM_POL : string := "RISING";
+    CLKOS_TRIM_DELAY : integer := 0;
+    OUTDIVIDER_MUXA : string := "DIVA";
+    OUTDIVIDER_MUXB : string := "DIVB";
+    OUTDIVIDER_MUXC : string := "DIVC";
+    OUTDIVIDER_MUXD : string := "DIVD";
+    PLL_LOCK_MODE : integer := 0;
+    PLL_LOCK_DELAY : integer := 200;
+    STDBY_ENABLE : string := "DISABLED";
+    REFIN_RESET : string := "DISABLED";
+    SYNC_ENABLE : string := "DISABLED";
+    INT_LOCK_STICKY : string := "ENABLED";
+    DPHASE_SOURCE : string := "DISABLED";
+    PLLRST_ENA : string := "DISABLED";
+    INTFB_WAKE : string := "DISABLED"  );
+  port (
+    CLKI :   in  std_logic;
+    CLKFB :   in  std_logic;
+    PHASESEL1 :   in  std_logic;
+    PHASESEL0 :   in  std_logic;
+    PHASEDIR :   in  std_logic;
+    PHASESTEP :   in  std_logic;
+    PHASELOADREG :   in  std_logic;
+    STDBY :   in  std_logic;
+    PLLWAKESYNC :   in  std_logic;
+    RST :   in  std_logic;
+    ENCLKOP :   in  std_logic;
+    ENCLKOS :   in  std_logic;
+    ENCLKOS2 :   in  std_logic;
+    ENCLKOS3 :   in  std_logic;
+    CLKOP :   out  std_logic;
+    CLKOS :   out  std_logic;
+    CLKOS2 :   out  std_logic;
+    CLKOS3 :   out  std_logic;
+    LOCK :   out  std_logic;
+    INTLOCK :   out  std_logic;
+    REFCLK :   out  std_logic;
+    CLKINTFB :   out  std_logic  );
 end component;
 
 component pllrefcs is
diff --git a/library/wrapper/bram.v b/library/wrapper/bram.v
index 03859dc..cd99939 100644
--- a/library/wrapper/bram.v
+++ b/library/wrapper/bram.v
@@ -1,7 +1,7 @@
 // Workaround BRAM implementation for fifo buffer
 // 2020 <hackfin@section5.ch>
 
-module bram_2psync_6_8_59fe624214af9b8daa183282288d5eb56b321f14 #(
+module bram_2psync #(
 	parameter DATA = 8,
 	parameter ADDR = 6
 ) (
diff --git a/testsuite/examples/test-ecp5_versa/testsuite.sh b/testsuite/examples/test-ecp5_versa/testsuite.sh
index 44dac88..8574b94 100755
--- a/testsuite/examples/test-ecp5_versa/testsuite.sh
+++ b/testsuite/examples/test-ecp5_versa/testsuite.sh
@@ -16,7 +16,6 @@ VHDL_SYN_FILES="$src/versa_ecp5_top.vhdl \
 
 VERILOG_FILES="\
  $top/library/wrapper/primitives.v \
- $top/library/wrapper/wrapper.v \
  $top/library/wrapper/bram.v
 "