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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:37:45 +0200 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:37:45 +0200 |
| commit | 31e54157acbceca921733da0a9fc521398f06e1b (patch) | |
| tree | c3eb9bddeb7b14a61497a6a319cea541e7276a9c /examples/ecp5_versa/Makefile | |
| parent | b47da302862e0e5510bb5ef285fa807574042f43 (diff) | |
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Handle Id_User_Parameters: add parameters to gates.
This allows easy interfacing with verilog modules.
Diffstat (limited to 'examples/ecp5_versa/Makefile')
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