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| author | Tristan Gingold <tgingold@free.fr> | 2020-01-20 07:03:07 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-01-20 07:03:42 +0100 |
| commit | bfb4f21519374e8ffb88813722a2d26308ec685c (patch) | |
| tree | 6f56b13603f9e22d0e5ff2991da22f658f8ee1ca /examples/ecp5_versa/uart_tx.vhdl | |
| parent | 910073d647e55d133494429d8c3a4bacffc32428 (diff) | |
| download | ghdl-yosys-plugin-bfb4f21519374e8ffb88813722a2d26308ec685c.tar.gz ghdl-yosys-plugin-bfb4f21519374e8ffb88813722a2d26308ec685c.tar.bz2 ghdl-yosys-plugin-bfb4f21519374e8ffb88813722a2d26308ec685c.zip | |
Make test logs mode consistent: Add OK status. For #79
Diffstat (limited to 'examples/ecp5_versa/uart_tx.vhdl')
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