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author | eine <6628437+eine@users.noreply.github.com> | 2020-01-19 03:25:43 +0000 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2020-01-19 04:25:43 +0100 |
commit | 910073d647e55d133494429d8c3a4bacffc32428 (patch) | |
tree | 6b1e616a1f670d44b03c1239ab5cba8aff15b909 /examples/icestick/multi2.vhdl | |
parent | 175123cda990ee2b5cfac461bd8ec44956da302a (diff) | |
download | ghdl-yosys-plugin-910073d647e55d133494429d8c3a4bacffc32428.tar.gz ghdl-yosys-plugin-910073d647e55d133494429d8c3a4bacffc32428.tar.bz2 ghdl-yosys-plugin-910073d647e55d133494429d8c3a4bacffc32428.zip |
migrate from Travis to GHA and rework examples (#78)
* migrate from Travis to GHA
* rework examples
Diffstat (limited to 'examples/icestick/multi2.vhdl')
-rw-r--r-- | examples/icestick/multi2.vhdl | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/examples/icestick/multi2.vhdl b/examples/icestick/multi2.vhdl new file mode 100644 index 0000000..78bf298 --- /dev/null +++ b/examples/icestick/multi2.vhdl @@ -0,0 +1,41 @@ +architecture multi2 of leds is + signal clk_4hz: std_logic; + signal clk_5sec : std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable counter5 : unsigned (4 downto 0); + begin + if rising_edge (clk) then + clk_5sec <= '0'; + if clk_4hz = '1' then + if counter5 = 19 then + clk_5sec <= '1'; + counter5 := "00000"; + else + counter5 := counter5 + 1; + end if; + end if; + end if; + end process; + + led1 <= clk_5sec; + led2 <= '0'; + led3 <= '0'; + led4 <= '0'; + led5 <= '0'; +end multi2; |