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authoreine <6628437+eine@users.noreply.github.com>2020-01-19 03:25:43 +0000
committertgingold <tgingold@users.noreply.github.com>2020-01-19 04:25:43 +0100
commit910073d647e55d133494429d8c3a4bacffc32428 (patch)
tree6b1e616a1f670d44b03c1239ab5cba8aff15b909 /examples/icestick/spin1.vhdl
parent175123cda990ee2b5cfac461bd8ec44956da302a (diff)
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migrate from Travis to GHA and rework examples (#78)
* migrate from Travis to GHA * rework examples
Diffstat (limited to 'examples/icestick/spin1.vhdl')
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diff --git a/examples/icestick/spin1.vhdl b/examples/icestick/spin1.vhdl
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+architecture spin1 of leds is
+ signal nrst : std_logic := '0';
+ signal clk_4hz: std_logic;
+ signal leds : std_ulogic_vector (1 to 5);
+begin
+ (led1, led2, led3, led4, led5) <= leds;
+
+ process (clk)
+ variable cnt : unsigned (1 downto 0) := "00";
+ begin
+ if rising_edge (clk) then
+ if cnt = 3 then
+ nrst <= '1';
+ else
+ cnt := cnt + 1;
+ end if;
+ end if;
+ end process;
+
+ process (clk)
+ -- 3_000_000 is 0x2dc6c0
+ variable counter : unsigned (23 downto 0);
+ begin
+ if rising_edge(clk) then
+ if nrst = '0' then
+ counter := x"000000";
+ else
+ if counter = 2_999_999 then
+ counter := x"000000";
+ clk_4hz <= '1';
+ else
+ counter := counter + 1;
+ clk_4hz <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ if nrst = '0' then
+ -- Initialize
+ leds <= "11000";
+ elsif clk_4hz = '1' then
+ -- Rotate
+ leds <= (leds (4), leds (1), leds (2), leds (3), '0');
+ end if;
+ end if;
+ end process;
+end spin1;