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authoreine <6628437+eine@users.noreply.github.com>2020-01-19 03:25:43 +0000
committertgingold <tgingold@users.noreply.github.com>2020-01-19 04:25:43 +0100
commit910073d647e55d133494429d8c3a4bacffc32428 (patch)
tree6b1e616a1f670d44b03c1239ab5cba8aff15b909 /examples/icezum/blink.vhdl
parent175123cda990ee2b5cfac461bd8ec44956da302a (diff)
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migrate from Travis to GHA and rework examples (#78)
* migrate from Travis to GHA * rework examples
Diffstat (limited to 'examples/icezum/blink.vhdl')
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diff --git a/examples/icezum/blink.vhdl b/examples/icezum/blink.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity blink is
+ port (
+ clk : in std_logic;
+ led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic
+ );
+end blink;
+
+architecture synth of blink is
+ signal blink: std_logic;
+begin
+ process (clk)
+ variable cnt : unsigned (23 downto 0); -- 3_000_000 requires 24 bits
+ begin
+ if rising_edge(clk) then
+ if cnt = 2_999_999 then
+ cnt := x"000000";
+ blink <= not blink;
+ else
+ cnt := cnt + 1;
+ end if;
+ end if;
+ end process;
+ led0 <= blink;
+ led1 <= blink;
+ led2 <= blink;
+ led3 <= blink;
+ led4 <= blink;
+ led5 <= blink;
+ led6 <= blink;
+ led7 <= blink;
+end synth;