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author | eine <6628437+eine@users.noreply.github.com> | 2020-01-19 03:25:43 +0000 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2020-01-19 04:25:43 +0100 |
commit | 910073d647e55d133494429d8c3a4bacffc32428 (patch) | |
tree | 6b1e616a1f670d44b03c1239ab5cba8aff15b909 /examples/icezum/counter.vhdl | |
parent | 175123cda990ee2b5cfac461bd8ec44956da302a (diff) | |
download | ghdl-yosys-plugin-910073d647e55d133494429d8c3a4bacffc32428.tar.gz ghdl-yosys-plugin-910073d647e55d133494429d8c3a4bacffc32428.tar.bz2 ghdl-yosys-plugin-910073d647e55d133494429d8c3a4bacffc32428.zip |
migrate from Travis to GHA and rework examples (#78)
* migrate from Travis to GHA
* rework examples
Diffstat (limited to 'examples/icezum/counter.vhdl')
-rw-r--r-- | examples/icezum/counter.vhdl | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/examples/icezum/counter.vhdl b/examples/icezum/counter.vhdl new file mode 100644 index 0000000..9cc4d7e --- /dev/null +++ b/examples/icezum/counter.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counter is + port ( + clk : in std_logic; + led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic + ); +end counter; + +architecture synth of counter is + signal clk_6hz : std_logic; +begin + -- Presscaler + prescaler: process(clk) + variable timer : unsigned (20 downto 0) := (others=>'0'); + begin + if rising_edge(clk) then + timer := timer + 1; + clk_6hz <= timer(20); + end if; + end process; + + -- 8 bits counter + process (clk_6hz) + variable temp : unsigned (7 downto 0); + begin + if rising_edge(clk_6hz) then + temp:= temp + 1; + -- Show the counter on the icezum Alhambra leds + (led7, led6, led5, led4, led3, led2, led1, led0) <= temp; + end if; + end process; +end synth; |