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authorTristan Gingold <tgingold@free.fr>2017-02-13 08:28:09 +0100
committerTristan Gingold <tgingold@free.fr>2017-02-13 08:28:09 +0100
commitd343b8fc2861db2dce9d860d517c6cc83acbdc75 (patch)
treeba97fac4dd7b0fb6159b0ecfdbc52ccb32afde89 /ghdl/ghdl.cc
parentc224fa3858309c22dea7f8ca50365bc22a65812f (diff)
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Fix for #4: a signal is not always the output of a gate.
Diffstat (limited to 'ghdl/ghdl.cc')
-rw-r--r--ghdl/ghdl.cc10
1 files changed, 6 insertions, 4 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc
index b4c26a8..78d1571 100644
--- a/ghdl/ghdl.cc
+++ b/ghdl/ghdl.cc
@@ -216,7 +216,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
case Id_Concat2:
case Id_Concat3:
case Id_Concat4:
- // Skip
+ // Skip: these won't create cells.
break;
default:
log_cmd_error("Unsupported(1): instance %s of %s.\n",
@@ -277,9 +277,11 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
case Id_Signal:
{
Net sig = get_driver(get_input(inst, 0));
- Wire *w = net_map.at(sig.id);
- if (w)
- module->rename(w, to_str(iname));
+ if (is_set(net_map, sig)) {
+ Wire *w = net_map.at(sig.id);
+ if (w)
+ module->rename(w, to_str(iname));
+ }
}
break;
case Id_Output: