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| author | Tristan Gingold <tgingold@free.fr> | 2017-02-15 12:22:54 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-02-15 12:22:54 +0100 |
| commit | 31c421981e03ef1861887507a9f19e2076a87fdb (patch) | |
| tree | 845a0bf514348181376a8dfd06854568cabb6b4c /ice40hx8k | |
| parent | 997b4da77c1a7002a7cd6f2794af88c8f8be7c52 (diff) | |
| download | ghdl-yosys-plugin-31c421981e03ef1861887507a9f19e2076a87fdb.tar.gz ghdl-yosys-plugin-31c421981e03ef1861887507a9f19e2076a87fdb.tar.bz2 ghdl-yosys-plugin-31c421981e03ef1861887507a9f19e2076a87fdb.zip | |
ice40hx8k/spin1.vhdl: assign all outputs.
Diffstat (limited to 'ice40hx8k')
| -rw-r--r-- | ice40hx8k/spin1.vhdl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/ice40hx8k/spin1.vhdl b/ice40hx8k/spin1.vhdl index 79e305c..7c50586 100644 --- a/ice40hx8k/spin1.vhdl +++ b/ice40hx8k/spin1.vhdl @@ -4,6 +4,9 @@ architecture spin1 of leds is signal leds : std_ulogic_vector (1 to 5); begin (led1, led2, led3, led4, led5) <= leds; + led6 <= '0'; + led7 <= '0'; + led8 <= '0'; process (clk) variable cnt : unsigned (1 downto 0) := "00"; |