Add examples

4 files changed, 101 insertions, 0 deletions

diff --git a/ice40hx8k/leds.vhdl b/ice40hx8k/leds.vhdl
new file mode 100644
index 0000000..557585b
--- /dev/null
+++ b/ice40hx8k/leds.vhdl
@@ -0,0 +1,8 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity leds is
+  port (clk : in std_logic;
+        led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic);
+end leds;
diff --git a/ice40hx8k/pinmap.pcf b/ice40hx8k/pinmap.pcf
new file mode 100644
index 0000000..6862c43
--- /dev/null
+++ b/ice40hx8k/pinmap.pcf
@@ -0,0 +1,13 @@
+# example.pcf
+set_io --warn-no-port led1 B5
+set_io --warn-no-port led2 B4
+set_io --warn-no-port led3 A2
+set_io --warn-no-port led4 A1
+set_io --warn-no-port led5 C5
+set_io --warn-no-port led6 C4
+set_io --warn-no-port led7 B3
+set_io --warn-no-port led8 C3
+set_io --warn-no-port clk J3
+# FTDI
+set_io --warn-no-port ftdi_tx B12
+set_io --warn-no-port ftdi_rx B10
diff --git a/ice40hx8k/spin1.vhdl b/ice40hx8k/spin1.vhdl
new file mode 100644
index 0000000..79e305c
--- /dev/null
+++ b/ice40hx8k/spin1.vhdl
@@ -0,0 +1,51 @@
+architecture spin1 of leds is
+  signal nrst : std_logic := '0';
+  signal clk_4hz: std_logic;
+  signal leds : std_ulogic_vector (1 to 5);
+begin
+  (led1, led2, led3, led4, led5) <= leds;
+
+  process (clk)
+    variable cnt : unsigned (1 downto 0) := "00";
+  begin
+    if rising_edge (clk) then
+      if cnt = 3 then
+        nrst <= '1';
+      else
+        cnt := cnt + 1;
+      end if;
+    end if;
+  end process;
+
+  process (clk)
+    --  3_000_000 is 0x2dc6c0
+    variable counter : unsigned (23 downto 0);
+  begin
+    if rising_edge(clk) then
+      if nrst = '0' then
+        counter := x"000000";
+      else
+        if counter = 2_999_999 then
+          counter := x"000000";
+          clk_4hz <= '1';
+        else
+          counter := counter + 1;
+          clk_4hz <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if nrst = '0' then
+        -- Initialize
+        leds <= "11000";
+      elsif clk_4hz = '1' then
+        --  Rotate
+        leds <= (leds (4), leds (1), leds (2), leds (3), '0');
+      end if;
+    end if;
+  end process;
+end spin1;
diff --git a/ice40hx8k/spin2.vhdl b/ice40hx8k/spin2.vhdl
new file mode 100644
index 0000000..ccdab8b
--- /dev/null
+++ b/ice40hx8k/spin2.vhdl
@@ -0,0 +1,29 @@
+architecture spin2 of leds is
+  signal clk_4hz: std_logic;
+  signal leds : std_ulogic_vector (1 to 8) := "11000000";
+begin
+  (led1, led2, led3, led4, led5, led6, led7, led8) <= leds;
+
+  process (clk)
+    --  3_000_000 is 0x2dc6c0
+    variable counter : unsigned (23 downto 0);
+  begin
+    if rising_edge(clk) then
+      if counter = 2_999_999 then
+        counter := x"000000";
+        clk_4hz <= '1';
+      else
+        counter := counter + 1;
+        clk_4hz <= '0';
+      end if;
+    end if;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) and clk_4hz = '1' then
+        --  Rotate
+      leds <= (leds (8), leds (1), leds (2), leds (3), leds (4), leds (5), leds (6), leds (7));
+    end if;
+  end process;
+end spin2;