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authorTristan Gingold <tgingold@free.fr>2017-02-02 21:35:01 +0100
committerTristan Gingold <tgingold@free.fr>2017-02-02 21:35:01 +0100
commitbd7e5c9457471bb24d825574c9aa3d9a3af63c03 (patch)
tree194781d16b082ae259f17dd8dc12b84b04ec7105 /icestick/rotate1.vhdl
parentfa2166d5bbf07ffc764b2e562f1eaf8ae3b4f1b6 (diff)
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Diffstat (limited to 'icestick/rotate1.vhdl')
-rw-r--r--icestick/rotate1.vhdl51
1 files changed, 51 insertions, 0 deletions
diff --git a/icestick/rotate1.vhdl b/icestick/rotate1.vhdl
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+architecture rotate1 of leds is
+ signal clk_4hz: std_logic;
+begin
+ process (clk)
+ -- 3_000_000 is 0x2dc6c0
+ variable counter : unsigned (23 downto 0);
+ begin
+ if rising_edge(clk) then
+ if counter = 2_999_999 then
+ counter := x"000000";
+ clk_4hz <= '1';
+ else
+ counter := counter + 1;
+ clk_4hz <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (clk)
+ variable count : unsigned (1 downto 0);
+ begin
+ if rising_edge(clk) and clk_4hz = '1' then
+ count := count + 1;
+ if count = 0 then
+ led1 <= '1';
+ led2 <= '0';
+ led3 <= '0';
+ led4 <= '0';
+ led5 <= '1';
+ elsif count = 1 then
+ led1 <= '0';
+ led2 <= '1';
+ led3 <= '0';
+ led4 <= '0';
+ led5 <= '0';
+ elsif count = 2 then
+ led1 <= '0';
+ led2 <= '0';
+ led3 <= '1';
+ led4 <= '0';
+ led5 <= '1';
+ else
+ led1 <= '0';
+ led2 <= '0';
+ led3 <= '0';
+ led4 <= '1';
+ led5 <= '0';
+ end if;
+ end if;
+ end process;
+end rotate1;