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author | marph91 <33229141+marph91@users.noreply.github.com> | 2019-08-22 20:45:38 +0200 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2019-08-22 20:45:38 +0200 |
commit | 4f3462be120ad924ae1f6df5cc59a2d0a87f459d (patch) | |
tree | 417c4140740244f682671392d7660a86b05965c9 /icestick/uart/hdl/uart_top.vhd | |
parent | d359d6deb55e5c51707c86263b090fabbc5c41b2 (diff) | |
download | ghdl-yosys-plugin-4f3462be120ad924ae1f6df5cc59a2d0a87f459d.tar.gz ghdl-yosys-plugin-4f3462be120ad924ae1f6df5cc59a2d0a87f459d.tar.bz2 ghdl-yosys-plugin-4f3462be120ad924ae1f6df5cc59a2d0a87f459d.zip |
Icestick uart (#37)
* added UART example for the icestick
* extended testsuite by the UART example
Diffstat (limited to 'icestick/uart/hdl/uart_top.vhd')
-rwxr-xr-x | icestick/uart/hdl/uart_top.vhd | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/icestick/uart/hdl/uart_top.vhd b/icestick/uart/hdl/uart_top.vhd new file mode 100755 index 0000000..889a3a0 --- /dev/null +++ b/icestick/uart/hdl/uart_top.vhd @@ -0,0 +1,49 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity uart_top is + generic ( + C_BITS : integer := 8 + ); + port ( + isl_clk : in std_logic; + isl_data_n : in std_logic; + osl_data_n : out std_logic; + osl_ready : out std_logic + ); +end uart_top; + +architecture behavioral of uart_top is + constant C_QUARTZ_FREQ : integer := 12000000; -- Hz + constant C_BAUDRATE : integer := 115200; -- words / s + constant C_CYCLES_PER_BIT : integer := C_QUARTZ_FREQ / C_BAUDRATE; + + signal sl_valid_out_tx : std_logic := '0'; + signal slv_data_out_tx : std_logic_vector(C_BITS-1 downto 0) := (others => '0'); + +begin + i_uart_rx: entity work.uart_rx + generic map ( + C_BITS => C_BITS, + C_CYCLES_PER_BIT => C_CYCLES_PER_BIT + ) + port map ( + isl_clk => isl_clk, + isl_data_n => isl_data_n, + oslv_data => slv_data_out_tx, + osl_valid => sl_valid_out_tx + ); + + i_uart_tx: entity work.uart_tx + generic map ( + C_BITS => C_BITS, + C_CYCLES_PER_BIT => C_CYCLES_PER_BIT + ) + port map ( + isl_clk => isl_clk, + isl_valid => sl_valid_out_tx, + islv_data => slv_data_out_tx, + osl_data_n => osl_data_n, + osl_ready => osl_ready + ); +end behavioral;
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