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| author | marph91 <33229141+marph91@users.noreply.github.com> | 2019-08-22 20:45:38 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-08-22 20:45:38 +0200 |
| commit | 4f3462be120ad924ae1f6df5cc59a2d0a87f459d (patch) | |
| tree | 417c4140740244f682671392d7660a86b05965c9 /icestick/uart/syn/constraints | |
| parent | d359d6deb55e5c51707c86263b090fabbc5c41b2 (diff) | |
| download | ghdl-yosys-plugin-4f3462be120ad924ae1f6df5cc59a2d0a87f459d.tar.gz ghdl-yosys-plugin-4f3462be120ad924ae1f6df5cc59a2d0a87f459d.tar.bz2 ghdl-yosys-plugin-4f3462be120ad924ae1f6df5cc59a2d0a87f459d.zip | |
Icestick uart (#37)
* added UART example for the icestick
* extended testsuite by the UART example
Diffstat (limited to 'icestick/uart/syn/constraints')
| -rwxr-xr-x | icestick/uart/syn/constraints/uart.pcf | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/icestick/uart/syn/constraints/uart.pcf b/icestick/uart/syn/constraints/uart.pcf new file mode 100755 index 0000000..e3e5016 --- /dev/null +++ b/icestick/uart/syn/constraints/uart.pcf @@ -0,0 +1,6 @@ +# FTDI Port B UART +set_io osl_data_n 8 # UART TX +set_io isl_data_n 9 # UART RX + +# 12 MHz clock +set_io isl_clk 21 |