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authoreine <6628437+eine@users.noreply.github.com>2020-01-19 03:25:43 +0000
committertgingold <tgingold@users.noreply.github.com>2020-01-19 04:25:43 +0100
commit910073d647e55d133494429d8c3a4bacffc32428 (patch)
tree6b1e616a1f670d44b03c1239ab5cba8aff15b909 /icezum/blink/blink.vhdl
parent175123cda990ee2b5cfac461bd8ec44956da302a (diff)
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migrate from Travis to GHA and rework examples (#78)
* migrate from Travis to GHA * rework examples
Diffstat (limited to 'icezum/blink/blink.vhdl')
-rw-r--r--icezum/blink/blink.vhdl35
1 files changed, 0 insertions, 35 deletions
diff --git a/icezum/blink/blink.vhdl b/icezum/blink/blink.vhdl
deleted file mode 100644
index 9279622..0000000
--- a/icezum/blink/blink.vhdl
+++ /dev/null
@@ -1,35 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity blink is
- port (clk : in std_logic;
- led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic);
-end blink;
-
-architecture synth of blink is
- signal clk_4hz: std_logic;
-begin
- process (clk)
- -- 3_000_000 is 0x2dc6c0
- variable counter : unsigned (23 downto 0);
- begin
- if rising_edge(clk) then
- if counter = 2_999_999 then
- counter := x"000000";
- clk_4hz <= not clk_4hz;
- else
- counter := counter + 1;
- end if;
- end if;
- end process;
-
- led0 <= clk_4hz;
- led1 <= clk_4hz;
- led2 <= clk_4hz;
- led3 <= clk_4hz;
- led4 <= clk_4hz;
- led5 <= clk_4hz;
- led6 <= clk_4hz;
- led7 <= clk_4hz;
-end synth;