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authorobijuan <juan@iearobotics.com>2017-02-11 11:31:45 +0100
committerobijuan <juan@iearobotics.com>2017-02-11 11:31:45 +0100
commitfefc6e76ffe3d88dfbd1badce83600e3cb919179 (patch)
treefa77f57064cc615090aa714c97d6f74ba0c56397 /icezum/blink/blink.vhdl
parent544101c7674cdc4d7dd06d4d401a444870143d48 (diff)
parent2e9f36985f1b320a8cf5d57fba40aa822cd0f6ab (diff)
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blink example for the icezum alhambra board added
Diffstat (limited to 'icezum/blink/blink.vhdl')
-rw-r--r--icezum/blink/blink.vhdl35
1 files changed, 35 insertions, 0 deletions
diff --git a/icezum/blink/blink.vhdl b/icezum/blink/blink.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity blink is
+ port (clk : in std_logic;
+ led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic);
+end blink;
+
+architecture synth of blink is
+ signal clk_4hz: std_logic;
+begin
+ process (clk)
+ -- 3_000_000 is 0x2dc6c0
+ variable counter : unsigned (23 downto 0);
+ begin
+ if rising_edge(clk) then
+ if counter = 2_999_999 then
+ counter := x"000000";
+ clk_4hz <= not clk_4hz;
+ else
+ counter := counter + 1;
+ end if;
+ end if;
+ end process;
+
+ led0 <= clk_4hz;
+ led1 <= clk_4hz;
+ led2 <= clk_4hz;
+ led3 <= clk_4hz;
+ led4 <= clk_4hz;
+ led5 <= clk_4hz;
+ led6 <= clk_4hz;
+ led7 <= clk_4hz;
+end synth;