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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-22 07:21:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-22 07:21:12 +0200 |
| commit | 8cb58b6d252084371ef6901acb67b5b706f7d504 (patch) | |
| tree | 530b150fa5c21c49289e696bc9baa1e1be43518b /src/ghdl.cc | |
| parent | 2141001bc795cd4fd12c9bb3a0f5d689c7840ef5 (diff) | |
| download | ghdl-yosys-plugin-8cb58b6d252084371ef6901acb67b5b706f7d504.tar.gz ghdl-yosys-plugin-8cb58b6d252084371ef6901acb67b5b706f7d504.tar.bz2 ghdl-yosys-plugin-8cb58b6d252084371ef6901acb67b5b706f7d504.zip | |
Handle Id_Cover_Assert
Diffstat (limited to 'src/ghdl.cc')
| -rw-r--r-- | src/ghdl.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index d0c3c35..01da606 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -466,6 +466,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Assert: // No output case Id_Assume: // No output case Id_Cover: // No output + case Id_Assert_Cover: // No output case Id_User_None: for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) { Net o = get_output(inst, idx); @@ -682,6 +683,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) module->addAssume(to_str(iname), IN(0), State::S1); break; case Id_Cover: + case Id_Assert_Cover: module->addCover(to_str(iname), IN(0), State::S1); break; case Id_Memory: |