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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-14 06:39:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-14 06:39:25 +0200 |
| commit | 90c54117cd27fcdc18ce18fb32a68062fa09e620 (patch) | |
| tree | 05a8e8def78750cf48c07969969552051bca2c85 /src/ghdl.cc | |
| parent | c9b05e481423c55ffcbb856fd5296701f670808c (diff) | |
| download | ghdl-yosys-plugin-90c54117cd27fcdc18ce18fb32a68062fa09e620.tar.gz ghdl-yosys-plugin-90c54117cd27fcdc18ce18fb32a68062fa09e620.tar.bz2 ghdl-yosys-plugin-90c54117cd27fcdc18ce18fb32a68062fa09e620.zip | |
ghdl.cc: handle dlatch
Diffstat (limited to 'src/ghdl.cc')
| -rw-r--r-- | src/ghdl.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index aa6f129..fb6cb8e 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -757,6 +757,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Idff: case Id_Adff: case Id_Iadff: + case Id_Dlatch: case Id_Eq: case Id_Ne: case Id_Ult: @@ -1089,6 +1090,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) } } break; + case Id_Dlatch: + module->addDlatch(to_str(iname), IN(1), IN(0), OUT(0)); + break; case Id_User_None: case Id_User_Parameters: { |