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author | Xiretza <Xiretza@users.noreply.github.com> | 2020-03-10 18:20:23 +0100 |
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committer | GitHub <noreply@github.com> | 2020-03-10 18:20:23 +0100 |
commit | d11471a86eebd0e041032bce74672744ec48ee61 (patch) | |
tree | 84bf28063e24841d64f29672b39e6bcaf1374f5d /src/ghdl.cc | |
parent | 33f046ca40aae8419e4ea3310cc0f76b537fdefe (diff) | |
download | ghdl-yosys-plugin-d11471a86eebd0e041032bce74672744ec48ee61.tar.gz ghdl-yosys-plugin-d11471a86eebd0e041032bce74672744ec48ee61.tar.bz2 ghdl-yosys-plugin-d11471a86eebd0e041032bce74672744ec48ee61.zip |
Add abs gate (#91)
Diffstat (limited to 'src/ghdl.cc')
-rw-r--r-- | src/ghdl.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 18facfe..9322ad8 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -557,6 +557,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Sgt: case Id_Sge: case Id_Not: + case Id_Abs: case Id_Red_Or: case Id_Red_And: case Id_Lsr: @@ -679,6 +680,14 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Not: module->addNot(to_str(iname), IN(0), OUT(0)); break; + case Id_Abs: + { + SigSpec isNegative = IN(0).extract(IN(0).size() - 1, 1); + RTLIL::Wire *negated = module->addWire(NEW_ID, IN(0).size()); + module->addNeg(NEW_ID, IN(0), negated); + module->addMux(NEW_ID, IN(0), negated, isNegative, OUT(0)); + } + break; case Id_Eq: module->addEq(to_str(iname), IN(0), IN(1), OUT(0)); break; |