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| author | Anton Blanchard <anton@ozlabs.org> | 2019-10-16 14:40:59 +1100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-16 05:40:59 +0200 |
| commit | b758bf4c7a5468dbf75972b767e3053b16768891 (patch) | |
| tree | db196a5fabe82c5b11d50ea57379b961f81103e8 /src | |
| parent | 62dd7c9e0f60d436c843bc7a654b9c60ef5871cc (diff) | |
| download | ghdl-yosys-plugin-b758bf4c7a5468dbf75972b767e3053b16768891.tar.gz ghdl-yosys-plugin-b758bf4c7a5468dbf75972b767e3053b16768891.tar.bz2 ghdl-yosys-plugin-b758bf4c7a5468dbf75972b767e3053b16768891.zip | |
Add Id_Smul and Id_Umul (#64)
* Add Id_Smul and Id_Umul support
* Add testcase for Id_Smul and Id_Umul
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 1d26ded..91239e5 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -306,6 +306,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Lsr: case Id_Lsl: case Id_Asr: + case Id_Smul: + case Id_Umul: case Id_Assert: // No output case Id_Assume: // No output case Id_Cover: // No output @@ -443,6 +445,12 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Asr: module->addSshr(to_str(iname), IN(0), IN(1), OUT(0), true); break; + case Id_Smul: + module->addMul(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Umul: + module->addMul(to_str(iname), IN(0), IN(1), OUT(0), false); + break; case Id_Mux2: module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0)); break; |