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| author | Xiretza <xiretza@xiretza.xyz> | 2020-03-21 20:51:03 +0100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2020-03-22 08:13:31 +0100 |
| commit | c975230114caebe442e0ec403796771caf70925d (patch) | |
| tree | dc0b9047ead4b79df095e3c22ed4f5dd4f7ac5aa /src | |
| parent | 63bb08a0893209bd0b1f13e9ab5c3e585ed43514 (diff) | |
| download | ghdl-yosys-plugin-c975230114caebe442e0ec403796771caf70925d.tar.gz ghdl-yosys-plugin-c975230114caebe442e0ec403796771caf70925d.tar.bz2 ghdl-yosys-plugin-c975230114caebe442e0ec403796771caf70925d.zip | |
Add min/max gates
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 9322ad8..28107d4 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -563,6 +563,10 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Lsr: case Id_Lsl: case Id_Asr: + case Id_Smin: + case Id_Umin: + case Id_Smax: + case Id_Umax: case Id_Smul: case Id_Umul: case Id_Sdiv: @@ -733,6 +737,23 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Asr: module->addSshr(to_str(iname), IN(0), IN(1), OUT(0), true); break; + case Id_Smin: + case Id_Umin: + case Id_Smax: + case Id_Umax: + { + bool is_signed = (id == Id_Smin || id == Id_Smax); + + RTLIL::Wire *select_rhs = module->addWire(NEW_ID); + if (id == Id_Smin || id == Id_Umin) { + module->addGt(NEW_ID, IN(0), IN(1), select_rhs, is_signed); + } else { + module->addLt(NEW_ID, IN(0), IN(1), select_rhs, is_signed); + } + + module->addMux(to_str(iname), IN(0), IN(1), select_rhs, OUT(0)); + } + break; case Id_Smul: module->addMul(to_str(iname), IN(0), IN(1), OUT(0), true); break; |