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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-09 07:27:27 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-09 07:27:27 +0200 |
| commit | e3036dcd6b0cdc8bf885d943a891d9c68c565934 (patch) | |
| tree | 5659eb9b0a800d11ad6087aa445d4c950df4fd44 /src | |
| parent | 762c8b588ed81560792db16b9f50f7941fff85a1 (diff) | |
| download | ghdl-yosys-plugin-e3036dcd6b0cdc8bf885d943a891d9c68c565934.tar.gz ghdl-yosys-plugin-e3036dcd6b0cdc8bf885d943a891d9c68c565934.tar.bz2 ghdl-yosys-plugin-e3036dcd6b0cdc8bf885d943a891d9c68c565934.zip | |
Remove Id_Insert (unused).
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 05ef521..421f1b4 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -111,21 +111,6 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) RTLIL::SigSpec res = IN(0); return res.extract(get_param_uns32(inst, 0), get_width(n)); } - case Id_Insert: - { - int pos = get_param_uns32(inst, 0); - RTLIL::SigSpec in0 = IN(0); - int size0 = in0.size(); - RTLIL::SigSpec in1 = IN(1); - int size1 = in1.size(); - RTLIL::SigSpec res; - - for (int i = 0; i < size0; i++) { - res.append((i >= pos && i < pos + size1) ? - in1[i - pos] : in0[i]); - } - return res; - } case Id_Concat2: case Id_Concat3: case Id_Concat4: @@ -308,7 +293,6 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Utrunc: case Id_Strunc: case Id_Extract: - case Id_Insert: case Id_Concat2: case Id_Concat3: case Id_Concat4: @@ -478,7 +462,6 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Utrunc: case Id_Strunc: case Id_Extract: - case Id_Insert: case Id_Concat2: case Id_Concat3: case Id_Concat4: |