Add tests/examples for dff (both pos and neg edge).

1 files changed, 23 insertions, 0 deletions

diff --git a/testsuite/examples/dff/adff.vhdl b/testsuite/examples/dff/adff.vhdl
new file mode 100644
index 0000000..f5638b8
--- /dev/null
+++ b/testsuite/examples/dff/adff.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity adff is
+	port(
+		clk : in std_logic;
+                rst : in std_logic;
+		d : in std_logic;
+		q : out std_logic
+	);
+end entity;
+
+architecture arch of adff is
+begin
+	process (clk, rst)
+	begin
+                if rst = '1' then
+                        q <= '1';
+		elsif rising_edge(clk) then
+			q <= d;
+		end if;
+	end process;
+end architecture;