testsuite: add a test for #2392

1 files changed, 22 insertions, 0 deletions

diff --git a/testsuite/ghdl-issues/issue2392b/psl_p_plus.vhdl b/testsuite/ghdl-issues/issue2392b/psl_p_plus.vhdl
new file mode 100644
index 0000000..522ce86
--- /dev/null
+++ b/testsuite/ghdl-issues/issue2392b/psl_p_plus.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity psl_p_plus is
+	generic(
+		DATA_BITS: natural := 8
+	);
+	port(
+		clk_in: in std_logic;
+		
+		a_in: in std_logic;
+		b_in: in std_logic;
+		c_in: in std_logic
+	);
+end;
+
+architecture psl of psl_p_plus is
+begin
+	default clock is rising_edge(clk_in);
+	
+	p_plus_psl: assert {a_in[+]; b_in} |-> {c_in};
+end;