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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-16 08:21:54 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-16 08:21:54 +0200 |
| commit | 98b805782fbe30bd05305c978f9f0fc1378be054 (patch) | |
| tree | ab08c8177f720d58a323a582be73d217f4c45782 /testsuite/ghdl-issues | |
| parent | 62dd5df344c6ff76554920b09dce40641e0faf8c (diff) | |
| download | ghdl-yosys-plugin-98b805782fbe30bd05305c978f9f0fc1378be054.tar.gz ghdl-yosys-plugin-98b805782fbe30bd05305c978f9f0fc1378be054.tar.bz2 ghdl-yosys-plugin-98b805782fbe30bd05305c978f9f0fc1378be054.zip | |
Add a test for inout port with default value.
Diffstat (limited to 'testsuite/ghdl-issues')
| -rw-r--r-- | testsuite/ghdl-issues/issue1312/ent.vhdl | 14 | ||||
| -rwxr-xr-x | testsuite/ghdl-issues/issue1312/testsuite.sh | 9 |
2 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/ghdl-issues/issue1312/ent.vhdl b/testsuite/ghdl-issues/issue1312/ent.vhdl new file mode 100644 index 0000000..efd68a5 --- /dev/null +++ b/testsuite/ghdl-issues/issue1312/ent.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + a : inout std_logic := '0'; + d_out : out std_logic + ); +end; + +architecture a of ent is +begin + d_out <= a; +end; diff --git a/testsuite/ghdl-issues/issue1312/testsuite.sh b/testsuite/ghdl-issues/issue1312/testsuite.sh new file mode 100755 index 0000000..42d4220 --- /dev/null +++ b/testsuite/ghdl-issues/issue1312/testsuite.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +topdir=../.. +. $topdir/testenv.sh + +synth_import --std=08 ent.vhdl -e + +clean +echo OK |