testsuite: add a test for ghdl/ghdl#1699

2 files changed, 50 insertions, 0 deletions

diff --git a/testsuite/ghdl-issues/issue1699/test2.vhdl b/testsuite/ghdl-issues/issue1699/test2.vhdl
new file mode 100644
index 0000000..ec330e5
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1699/test2.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2 is
+    port (
+        clk  : in std_ulogic;
+        addr : in std_ulogic_vector(4 downto 0);
+        data : out std_ulogic_vector(2 downto 0)
+    );
+end entity test2;
+
+architecture rtl of test2 is
+    type result_t is array(integer range 0 to 15) of std_ulogic_vector(2 downto 0);
+
+    constant result_select : result_t := (
+        0      => "001",
+        1      => "001",
+        2      => "001",
+        3      => "001",
+        4      => "001",
+        5      => "001",
+        6      => "001",
+        7      => "001",
+        others => "000"
+        );
+begin
+
+    --lookup_0: process(all)
+    --begin
+        --data <= result_select(to_integer(unsigned(addr)));
+    --end process;
+
+    lookup_0: process(clk)
+    begin
+        if rising_edge(clk) then
+            data <= result_select(to_integer(unsigned(addr)));
+        end if;
+    end process;
+end;
+
diff --git a/testsuite/ghdl-issues/issue1699/testsuite.sh b/testsuite/ghdl-issues/issue1699/testsuite.sh
new file mode 100755
index 0000000..2636855
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1699/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -p "ghdl --std=08 test2.vhdl -e; write_verilog test2.v"
+
+clean
+echo OK