Add testcase for #11

1 files changed, 14 insertions, 0 deletions

diff --git a/testsuite/issue11/test_or.vhdl b/testsuite/issue11/test_or.vhdl
new file mode 100644
index 0000000..d39d064
--- /dev/null
+++ b/testsuite/issue11/test_or.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_or is port (
+    sel0, sel1: in std_logic;
+    c: out std_logic);
+end test_or;
+
+architecture synth of test_or is
+begin
+
+    c <= sel1 or sel0;
+
+end synth;