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| author | Xiretza <xiretza@xiretza.xyz> | 2020-04-08 22:29:46 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2020-05-30 19:20:32 +0200 |
| commit | d216549165da5496da30ce0a28fcf5c2a36a3278 (patch) | |
| tree | 70bfd9e8011f58f9a90df3a488871229901fd7d2 /testsuite/issues/bug-loop1 | |
| parent | 0b687cd21c5dc7bad4fe49f7d2554d1ddc542d17 (diff) | |
| download | ghdl-yosys-plugin-d216549165da5496da30ce0a28fcf5c2a36a3278.tar.gz ghdl-yosys-plugin-d216549165da5496da30ce0a28fcf5c2a36a3278.tar.bz2 ghdl-yosys-plugin-d216549165da5496da30ce0a28fcf5c2a36a3278.zip | |
Fix signed modulo behaviour
Yosys' $mod cell is the modulo of truncating division, known as "rem" in
VHDL.
The new $modfloor cell is the modulo of flooring division, known as "mod"
in VHDL.
"mod" now synthesizes correctly for negative numbers.
Diffstat (limited to 'testsuite/issues/bug-loop1')
0 files changed, 0 insertions, 0 deletions