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| author | T. Meissner <programming@goodcleanfun.de> | 2019-10-07 19:13:46 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-07 19:13:46 +0200 |
| commit | b405a27654f326eb1117c0eda8e7389a64fc5c94 (patch) | |
| tree | 87867ece999abba761b40ea5d2debdd6018247f4 /testsuite/issues/issue6/vector.vhdl | |
| parent | bf8b41da7f0650d93b79447a2a62313b15afc9af (diff) | |
| download | ghdl-yosys-plugin-b405a27654f326eb1117c0eda8e7389a64fc5c94.tar.gz ghdl-yosys-plugin-b405a27654f326eb1117c0eda8e7389a64fc5c94.tar.bz2 ghdl-yosys-plugin-b405a27654f326eb1117c0eda8e7389a64fc5c94.zip | |
testsuite: Add formal tests (#57)
* Add formal tests for shift operations
* ci: build ghdl/synth:formal and run test suites in it
* add testsuite/formal/testsuite.sh
* create testsuite/issues
* ci: remove a level of grouping
* testenv: fix SYMBIYOSYS
* refactor
* testsuite/formal/shifts: Add check for shifts > vector length
Diffstat (limited to 'testsuite/issues/issue6/vector.vhdl')
| -rw-r--r-- | testsuite/issues/issue6/vector.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/issues/issue6/vector.vhdl b/testsuite/issues/issue6/vector.vhdl new file mode 100644 index 0000000..255c0b5 --- /dev/null +++ b/testsuite/issues/issue6/vector.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port (led0: out std_logic); +end vector; + +architecture synth of vector is + +signal v : std_logic_vector(7 downto 0); + +begin + v <= std_logic_vector'("10101010"); + led0 <= v(1); --- But led0 <= v(0) works ok +end synth; |