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authorTristan Gingold <tgingold@free.fr>2019-11-06 03:55:50 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-06 03:55:50 +0100
commit690470aa7380ce198bfa170977a0932b83123a72 (patch)
tree2b5b0e29ee39d99e102216dd2b3f7a9262199e4e /testsuite/issues
parent4d1d02bc7e777a39122fdeefaa4559615c1d106d (diff)
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testsuite: reduce verbosity.
Diffstat (limited to 'testsuite/issues')
-rwxr-xr-xtestsuite/issues/issue68/testsuite.sh2
-rwxr-xr-xtestsuite/issues/issue7/testsuite.sh2
2 files changed, 2 insertions, 2 deletions
diff --git a/testsuite/issues/issue68/testsuite.sh b/testsuite/issues/issue68/testsuite.sh
index 9348be4..7c3a75a 100755
--- a/testsuite/issues/issue68/testsuite.sh
+++ b/testsuite/issues/issue68/testsuite.sh
@@ -3,6 +3,6 @@
topdir=../..
. $topdir/testenv.sh
-synth "demux.vhdl -e"
+synth_ice40 "demux.vhdl -e"
clean
diff --git a/testsuite/issues/issue7/testsuite.sh b/testsuite/issues/issue7/testsuite.sh
index 5d396dc..2ca1ccb 100755
--- a/testsuite/issues/issue7/testsuite.sh
+++ b/testsuite/issues/issue7/testsuite.sh
@@ -6,7 +6,7 @@ topdir=../..
run_yosys -Q -q -p "ghdl ref.vhdl -e vector ref; write_verilog ref.v"
run_yosys -Q -q -p "ghdl ref.vhdl vector.vhdl -e vector synth; write_verilog vector.v"
-run_yosys -Q -p '
+run_yosys -q -p '
read_verilog ref.v
rename vector ref