Add a test for #96

2 files changed, 33 insertions, 0 deletions

diff --git a/testsuite/issues/issue96/ent.vhdl b/testsuite/issues/issue96/ent.vhdl
new file mode 100644
index 0000000..8f2f1b5
--- /dev/null
+++ b/testsuite/issues/issue96/ent.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        a      : inout std_logic;
+        enable : in std_logic;
+        d_in   : in std_logic;
+        d_out  : out std_logic
+    );
+end;
+
+architecture a of ent is
+begin
+    process(all)
+    begin
+        if enable then
+            a <= d_in;
+        else
+            a <= 'Z';
+        end if;
+    end process;
+    d_out <= a;
+end;
diff --git a/testsuite/issues/issue96/testsuite.sh b/testsuite/issues/issue96/testsuite.sh
new file mode 100755
index 0000000..42d4220
--- /dev/null
+++ b/testsuite/issues/issue96/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+synth_import --std=08 ent.vhdl -e
+
+clean
+echo OK