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authorTristan Gingold <tgingold@free.fr>2020-08-04 06:38:24 +0200
committerTristan Gingold <tgingold@free.fr>2020-09-27 09:57:18 +0200
commit987f573390666b057b2275ddda3c0f0ef70303c4 (patch)
tree26bf69b71429b7889d702581bd85ae68cb42930d /testsuite
parent8aae9102038582e702b5d68d30a48b3aefff6810 (diff)
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testsuite: add a test for ghdl/ghdl#1421
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/ghdl-issues/issue1421a/aes_pkg.vhdl40
-rw-r--r--testsuite/ghdl-issues/issue1421a/cipher.vhdl84
-rwxr-xr-xtestsuite/ghdl-issues/issue1421a/testsuite.sh9
3 files changed, 133 insertions, 0 deletions
diff --git a/testsuite/ghdl-issues/issue1421a/aes_pkg.vhdl b/testsuite/ghdl-issues/issue1421a/aes_pkg.vhdl
new file mode 100644
index 0000000..8873d82
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1421a/aes_pkg.vhdl
@@ -0,0 +1,40 @@
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+package aes_pkg is
+
+ type t_usig_1d is array(natural range <>) of unsigned(7 downto 0);
+
+ type t_usig_2d is array(natural range <>, natural range <>) of unsigned(7 downto 0);
+
+ constant C_STATE_ROWS : integer := 2;
+ constant C_STATE_COLS : integer := 2;
+
+ subtype st_word is t_usig_1d(0 to C_STATE_COLS - 1);
+ subtype st_state is t_usig_2d(0 to C_STATE_ROWS - 1, 0 to C_STATE_COLS - 1);
+ subtype st_sbox is t_usig_1d(0 to 255);
+
+ type t_key is array(natural range <>) of st_word;
+
+ function mix_columns (a_in : st_state) return st_state;
+
+end package aes_pkg;
+
+package body aes_pkg is
+
+ -- FIPS 197, 5.1.3 MixColumns() Transformation
+
+ function mix_columns (a_in : st_state) return st_state is
+ variable a_out : st_state;
+ begin
+ for col in 0 to C_STATE_COLS - 1 loop
+ a_out(0, col) := a_in(0, col) xor
+ a_in(1, col);
+ a_out(1, col) := a_in(0, col) xor
+ a_in(1, col);
+ end loop;
+ return a_out;
+ end mix_columns;
+end package body;
diff --git a/testsuite/ghdl-issues/issue1421a/cipher.vhdl b/testsuite/ghdl-issues/issue1421a/cipher.vhdl
new file mode 100644
index 0000000..5434a7e
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1421a/cipher.vhdl
@@ -0,0 +1,84 @@
+-- cipher module, as described in: "FIPS 197, 5.1 Cipher"
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library aes_lib;
+ use aes_lib.aes_pkg.all;
+
+entity cipher is
+ generic (
+ G_KEY_WORDS : integer := 4
+ );
+ port (
+ isl_clk : in std_logic;
+ isl_valid : in std_logic;
+ ia_data : in st_state;
+ ia_key : in t_key(0 to G_KEY_WORDS - 1);
+ oa_data : out st_state;
+ osl_valid : out std_logic
+ );
+end entity cipher;
+
+architecture rtl of cipher is
+
+ -- states
+ signal slv_stage : std_logic_vector(1 to 2) := (others => '0');
+ signal sl_next_round : std_logic := '0';
+
+ -- data container
+ -- data format in key expansion: words are rows
+ -- data format in cipher: words are columns
+ -- conversion: transpose matrix
+ signal a_data_in : st_state;
+ signal a_data_added : st_state;
+ signal a_data_srows : st_state;
+
+ -- keys
+ signal a_round_keys : st_state;
+ signal int_round_cnt : integer range 0 to 13 := 0;
+
+begin
+
+ sl_next_round <= slv_stage(2);
+
+ proc_key_expansion : process (isl_clk) is
+
+ variable v_new_col : integer range 0 to C_STATE_COLS - 1;
+ variable v_data_sbox : st_state;
+ variable v_data_mcols : st_state;
+
+ begin
+
+ if (rising_edge(isl_clk)) then
+ slv_stage <= (isl_valid or sl_next_round) & slv_stage(1);
+
+ -- substitute bytes and shift rows
+ if (slv_stage(1) = '1') then
+ for row in 0 to C_STATE_ROWS - 1 loop
+ for col in 0 to 0 loop --C_STATE_COLS - 1 loop
+ -- substitute bytes
+-- v_data_sbox(row, col) := C_SBOX(to_integer(a_data_added(row, col)));
+ v_data_sbox(row, col) := a_data_added(row, col);
+
+ -- shift rows
+ -- avoid modulo by using unsigned overflow
+ v_new_col := to_integer(to_unsigned(col, 1) - row);
+ a_data_srows(row, v_new_col) <= v_data_sbox(row, col);
+ end loop;
+ end loop;
+ end if;
+
+ -- mix columns and add key
+ if (slv_stage(2) = '1') then
+ a_data_added <= mix_columns(a_data_srows);
+ end if;
+ end if;
+
+ end process proc_key_expansion;
+
+ oa_data <= a_data_added;
+ osl_valid <= '0';
+
+end architecture rtl;
diff --git a/testsuite/ghdl-issues/issue1421a/testsuite.sh b/testsuite/ghdl-issues/issue1421a/testsuite.sh
new file mode 100755
index 0000000..20e3db7
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1421a/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+synth_import --std=08 --work=aes_lib aes_pkg.vhdl cipher.vhdl -e
+
+clean
+echo OK