Add Id_Smul and Id_Umul (#64)

* Add Id_Smul and Id_Umul support

* Add testcase for Id_Smul and Id_Umul

2 files changed, 26 insertions, 0 deletions

diff --git a/testsuite/pr64/testsuite.sh b/testsuite/pr64/testsuite.sh
new file mode 100755
index 0000000..7c3865a
--- /dev/null
+++ b/testsuite/pr64/testsuite.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+. ../testenv.sh
+
+run_yosys -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
+
+grep -q 11111111111011110000000000100000000000001101111111110000000000000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1
+grep -q 00000000000000000000000000001111111111111110111111110000000100000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1
+
+clean
diff --git a/testsuite/pr64/vector.vhdl b/testsuite/pr64/vector.vhdl
new file mode 100644
index 0000000..c88c117
--- /dev/null
+++ b/testsuite/pr64/vector.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (
+        s : out signed(127 downto 0);
+        u : out unsigned(127 downto 0)
+        );
+end entity vector;
+
+architecture synth of vector is
+begin
+    s <= signed'(x"ffff000000fffff0") * signed'(x"fff0000ffff00000");
+    u <= unsigned'(x"ffff000000fffff0") * unsigned'(x"fff0000ffff00000");
+end synth;