Run testsuite in Travis CI with docker images (#31)

* makefile: use '--build' shortcut to build ghdl.so

* move: rename subdir 'ghdl' to 'src'

* travis: add travis config file, build script and utils script

* testsuite: do not call ghdl explicitly

* readme: update

10 files changed, 40 insertions, 73 deletions

diff --git a/testsuite/issue11/testsuite.sh b/testsuite/issue11/testsuite.sh
index d0f9360..e281ee9 100755
--- a/testsuite/issue11/testsuite.sh
+++ b/testsuite/issue11/testsuite.sh
@@ -2,19 +2,8 @@
 
 . ../testenv.sh
 
-analyze test_or.vhdl
-synth test_or
-
-analyze test_xor.vhdl
-synth test_xor
-
-analyze test_nor.vhdl
-synth test_nor
-
-analyze test_nand.vhdl
-synth test_nand
-
-analyze test_xnor.vhdl
-synth test_xnor
+for f in or xor nor nand xnor; do
+  synth "test_${f}.vhdl -e test_${f}"
+done
 
 clean
diff --git a/testsuite/issue4/novector.vhdl b/testsuite/issue4/no_vector.vhdl
index a3c2c46..a3c2c46 100644
--- a/testsuite/issue4/novector.vhdl
+++ b/testsuite/issue4/no_vector.vhdl
diff --git a/testsuite/issue4/testsuite.sh b/testsuite/issue4/testsuite.sh
index 9eaedbc..49ead4d 100755
--- a/testsuite/issue4/testsuite.sh
+++ b/testsuite/issue4/testsuite.sh
@@ -2,13 +2,8 @@
 
 . ../testenv.sh
 
-analyze novector.vhdl
-synth no_vector
-
-analyze counter8.vhdl
-synth counter8
-
-analyze vector.vhdl
-synth vector
+for f in no_vector counter8 vector; do
+  synth "${f}.vhdl -e ${f}"
+done
 
 clean
diff --git a/testsuite/issue6/testsuite.sh b/testsuite/issue6/testsuite.sh
index 802618d..c1b6e25 100755
--- a/testsuite/issue6/testsuite.sh
+++ b/testsuite/issue6/testsuite.sh
@@ -2,7 +2,6 @@
 
 . ../testenv.sh
 
-analyze vector.vhdl
-synth vector
+synth 'vector.vhdl -e vector'
 
 clean
diff --git a/testsuite/issue7/testsuite.sh b/testsuite/issue7/testsuite.sh
index 939f28a..bdafcca 100755
--- a/testsuite/issue7/testsuite.sh
+++ b/testsuite/issue7/testsuite.sh
@@ -2,13 +2,10 @@
 
 . ../testenv.sh
 
-analyze ref.vhdl
-run_yosys -q -p "ghdl vector ref; write_verilog ref.v"
+run_yosys -Q -q -p "ghdl ref.vhdl -e vector ref; write_verilog ref.v"
+run_yosys -Q -q -p "ghdl ref.vhdl vector.vhdl -e vector synth; write_verilog vector.v"
 
-analyze vector.vhdl
-run_yosys -q -p "ghdl vector synth; write_verilog vector.v"
-
-run_yosys -p '
+run_yosys -Q -p '
  read_verilog ref.v
  rename vector ref
 
diff --git a/testsuite/test-ice40hx8k/testsuite.sh b/testsuite/test-ice40hx8k/testsuite.sh
index be1bf88..a14dcf8 100755
--- a/testsuite/test-ice40hx8k/testsuite.sh
+++ b/testsuite/test-ice40hx8k/testsuite.sh
@@ -2,11 +2,9 @@
 
 . ../testenv.sh
 
-analyze ../../ice40hx8k/leds.vhdl
-analyze ../../ice40hx8k/spin1.vhdl
-synth leds
+src=../../ice40hx8k
 
-analyze ../../ice40hx8k/spin2.vhdl
-synth leds
+synth "$src/leds.vhdl $src/spin1.vhdl -e leds"
+synth "$src/leds.vhdl $src/spin2.vhdl -e leds"
 
 clean
diff --git a/testsuite/test-icestick/testsuite.sh b/testsuite/test-icestick/testsuite.sh
index 889f5b3..99bf9eb 100755
--- a/testsuite/test-icestick/testsuite.sh
+++ b/testsuite/test-icestick/testsuite.sh
@@ -4,24 +4,10 @@
 
 src=../../icestick
 
-analyze $src/leds.vhdl
+# spin2
 
-files="fixed1.vhdl
- fixed1.vhdl
- blink.vhdl
- multi1.vhdl
- multi2.vhdl
- spin1.vhdl
- rotate1.vhdl
- rotate2.vhdl
- rotate3.vhdl
- rotate4.vhdl
-"
-# spin2.vhdl
-
-for f in $files; do
- analyze $src/$f
- synth leds
+for f in fixed1 blink multi1 multi2 spin1 rotate1 rotate2 rotate3 rotate4; do
+ synth "$src/leds.vhdl $src/${f}.vhdl -e leds"
 done
 
 clean
diff --git a/testsuite/test-icezum/testsuite.sh b/testsuite/test-icezum/testsuite.sh
index a3a71e5..3b6f620 100755
--- a/testsuite/test-icezum/testsuite.sh
+++ b/testsuite/test-icezum/testsuite.sh
@@ -2,16 +2,11 @@
 
 . ../testenv.sh
 
-analyze ../../icezum/led_on/led_on.vhdl
-synth led_on
+src=../../icezum
 
-analyze ../../icezum/blink/blink.vhdl
-synth blink
-
-analyze ../../icezum/pushbutton/pushbutton.vhdl
-synth pushbutton
-
-analyze ../../icezum/pushbutton_and/pushbutton_and.vhdl
-synth pushbutton_and
+synth "$src/led_on/led_on.vhdl -e led_on"
+synth "$src/blink/blink.vhdl -e blink"
+synth "$src/pushbutton/pushbutton.vhdl -e pushbutton"
+synth "$src/pushbutton_and/pushbutton_and.vhdl -e pushbutton_and"
 
 clean
diff --git a/testsuite/testenv.sh b/testsuite/testenv.sh
index 152f986..23c67e0 100644
--- a/testsuite/testenv.sh
+++ b/testsuite/testenv.sh
@@ -2,6 +2,8 @@
 
 set -e
 
+. ../../utils.sh
+
 if [ x"$GHDL" = x ]; then
     GHDL=ghdl
 fi
@@ -12,30 +14,32 @@ fi
 
 cmd ()
 {
-    echo "$@"
+    echo "· $@"
     "$@"
 }
 
 run_yosys ()
 {
-    cmd $YOSYS -Q "$@"
+    cmd $YOSYS "$@"
 }
 
 analyze ()
 {
-    echo "analyze $@"
+    printf "${ANSI_BLUE}Analyze $@ $ANSI_NOCOLOR\n"
     cmd "$GHDL" -a $GHDL_STD_FLAGS $GHDL_FLAGS $@
 }
 
 synth ()
 {
-    echo "synthesize $@"
-    run_yosys -q -p "ghdl $@; synth_ice40 -blif out.blif"
+    travis_start "synth" "Synthesize $@"
+    run_yosys -p "ghdl $@; synth_ice40 -blif out.blif"
+    travis_finish "synth"
 }
 
 clean ()
 {
-    echo "Remove work library"
+    travis_start "rm" "Remove work library"
     "$GHDL" --remove $GHDL_STD_FLAGS
     rm -f out.blif
+    travis_finish "rm"
 }
diff --git a/testsuite/testsuite.sh b/testsuite/testsuite.sh
index a2bfad8..943c66e 100755
--- a/testsuite/testsuite.sh
+++ b/testsuite/testsuite.sh
@@ -1,20 +1,24 @@
 #!/bin/sh
 
+cd "$(dirname $0)"
+. ../utils.sh
+
 for d in */; do
     if [ -f $d/testsuite.sh ]; then
-        echo "############ $d"
+        travis_start "test" "$d" "$ANSI_CYAN"
         cd $d
         if ./testsuite.sh; then
-            echo "OK"
+            printf "${ANSI_GREEN}OK$ANSI_NOCOLOR\n"
         else
-            echo "FAILED!"
+            printf "${ANSI_RED}FAILED!$ANSI_NOCOLOR\n"
             exit 1
         fi
         cd ..
+        travis_finish "test"
     else
-        echo "#### Skip $d (no testsuite.sh)"
+        printf "${ANSI_YELLOW}Skip $d (no testsuite.sh)$ANSI_NOCOLOR\n"
     fi
 done
 
-echo "All tests are OK"
+printf "${ANSI_GREEN}All tests are OK$ANSI_NOCOLOR\n"
 exit 0