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-rw-r--r--ghdl/ghdl.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc
index c0cfc40..e3da584 100644
--- a/ghdl/ghdl.cc
+++ b/ghdl/ghdl.cc
@@ -66,6 +66,7 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n)
switch(get_id(inst)) {
#define IN(N) get_src(net_map, get_input_net(inst, (N)))
case Id_Signal:
+ case Id_Isignal:
case Id_Port:
return IN(0);
case Id_Uextend:
@@ -254,6 +255,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
}
break;
case Id_Signal:
+ case Id_Isignal:
case Id_Output:
case Id_Port:
case Id_Const_UB32:
@@ -387,6 +389,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
break;
}
case Id_Signal:
+ case Id_Isignal:
{
Net sig = get_input_net(inst, 0);
if (is_set(net_map, sig)) {